公开(公告)号：US11488918B2

公开(公告)日：2022-11-01

申请号：US16177022

申请日：2018-10-31

Applicant: Intel Corporation

Inventor： Kristof Darmawaikarta ,  Robert May ,  Sashi Kandanur ,  Sri Ranga Sai Boyapati ,  Srinivas Pietambaram ,  Steve Cho ,  Jung Kyu Han ,  Thomas Heaton ,  Ali Lehaf ,  Ravindranadh Eluri ,  Hiroki Tanaka ,  Aleksandar Aleksov ,  Dilan Seneviratne

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/522 ,  H01L21/768

Abstract: Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).

公开(公告)号：US11421376B2

公开(公告)日：2022-08-23

申请号：US16072165

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Feras Eid ,  Aleksandar Aleksov ,  Sasha N. Oster ,  Baris Bicen ,  Thomas L. Sounart ,  Valluri R. Rao ,  Johanna M. Swan

IPC: H01L41/047 ,  D06M10/06 ,  D06M11/46 ,  D06M11/47 ,  H01L41/316 ,  D06M17/00 ,  H01L41/087 ,  D06M11/83 ,  H01L41/187 ,  H01L41/29 ,  D01F11/00

Abstract: Embodiments of the invention include an active fiber with a piezoelectric layer that has a crystallization temperature that is greater than a melt or draw temperature of the fiber and methods of forming such active fibers. According to an embodiment, a first electrode is formed over an outer surface of a fiber. Embodiments may then include depositing a first amorphous piezoelectric layer over the first electrode. Thereafter, the first amorphous piezoelectric layer may be crystallized with a pulsed laser annealing process to form a first crystallized piezoelectric layer. In an embodiment, the pulsed laser annealing process may include exposing the first amorphous piezoelectric layer to radiation from an excimer laser with an energy density between approximately 10 and 100 mJ/cm2 and pulse width between approximately 10 and 50 nanoseconds. Embodiments may also include forming a second electrode over an outer surface of the crystallized piezoelectric layer.

公开(公告)号：US11387187B2

公开(公告)日：2022-07-12

申请号：US16021966

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Andrew Paul Collins ,  Jianyong Xie ,  Sujit Sharan ,  Henning Braunisch ,  Aleksandar Aleksov

IPC: H01L23/495 ,  H01L23/053 ,  H01L23/48 ,  H01L21/4763 ,  H01L23/538 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L25/07

Abstract: Embodiments may relate to an interposer that has a first layer with a plurality of first layer pads that may couple with a die. The interposer may further include a second layer with a power delivery component. The interposer may further include a very high density (VHD) layer, that has a VHD pad coupled by a first via with the power delivery component and coupled by a second via with a first layer pad. Other embodiments may be described and/or claimed.

公开(公告)号：US20220201843A1

公开(公告)日：2022-06-23

申请号：US17695118

申请日：2022-03-15

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H05K1/02 ,  H05K1/16 ,  H05K3/12 ,  H05K3/40 ,  H05K9/00

Abstract: Embodiments may relate to a microelectronic package or a die thereof which includes a die, logic, or subsystem coupled with a face of the substrate. An inductor may be positioned in the substrate. Electromagnetic interference (EMI) shield elements may be positioned within the substrate and surrounding the inductor. Other embodiments may be described or claimed.

公开(公告)号：US20220189861A1

公开(公告)日：2022-06-16

申请号：US17121093

申请日：2020-12-14

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Mohammad Enamul Kabir ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan ,  Feras Eid

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components coupled by direct bonding, and related structures and techniques. In some embodiments, a microelectronic assembly may include a first microelectronic component including a first guard ring extending through at least a portion of a thickness of and along a perimeter; a second microelectronic component including a second guard ring extending through at least a portion of a thickness of and along a perimeter, where the first and second microelectronic components are coupled by direct bonding; and a seal ring formed by coupling the first guard ring to the second guard ring. In some embodiments, a microelectronic assembly may include a microelectronic component coupled to an interposer that includes a first liner material at a first surface; a second liner material at an opposing second surface; and a perimeter wall through the interposer and connected to the first and second liner materials.

公开(公告)号：US20220181166A1

公开(公告)日：2022-06-09

申请号：US17677105

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Kristof Kuwawi Darmawikarta ,  Robert May ,  Sri Ranga Sai Boyapati ,  Srinivas V. Pietambaram ,  Chung Kwang Christopher Tan ,  Aleksandar Aleksov

IPC: H01L21/48 ,  H01L23/498

Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.

公开(公告)号：US11348882B2

公开(公告)日：2022-05-31

申请号：US16683125

申请日：2019-11-13

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Feras Eid ,  Johanna M. Swan ,  Adel A. Elsherbini ,  Veronica Aleman Strong

IPC: H01L23/60 ,  H01L23/498 ,  H01L23/053 ,  H01L23/00

Abstract: Embodiments may relate to a microelectronic package with an electrostatic discharge (ESD) protection structure within the package substrate. The ESD protection structure may include a cavity that has a contact of a signal line and a contact of a ground line positioned therein. Other embodiments may be described or claimed.

公开(公告)号：US11309619B2

公开(公告)日：2022-04-19

申请号：US16327811

申请日：2016-09-23

Applicant: INTEL CORPORATION

Inventor： Sasha Oster ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Adel Elsherbini ,  Shawna Liff ,  Aleksandar Aleksov ,  Johanna Swan

IPC: H01L23/66 ,  H01Q1/22 ,  H01Q21/06 ,  H01Q21/00 ,  H01P5/18

Abstract: A waveguide coupling system may include at least one waveguide member retention structure disposed on an exterior surface of a semiconductor package. The waveguide member retention structure may be disposed a defined distance or at a defined location with respect to an antenna carried by the semiconductor package. The waveguide member retention structure may engage and guide a waveguide member slidably inserted into the respective waveguide member retention structure. The waveguide member retention structure may position the waveguide member at a defined location with respect to the antenna to maximize the power transfer from the antenna to the waveguide member.

公开(公告)号：US11296040B2

公开(公告)日：2022-04-05

申请号：US16721442

申请日：2019-12-19

Applicant: INTEL CORPORATION

Inventor： Adel A. Elsherbini ,  Feras Eid ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Veronica Aleman Strong

IPC: H01L21/00 ,  H01L23/60 ,  H01L23/48 ,  H01L27/02 ,  H01L23/00 ,  H01L23/498

Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). For example, in some embodiments, an IC package support may include: a first conductive structure in a dielectric material; a second conductive structure in the dielectric material; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a polymer, and the material is different from the dielectric material. The material may act as a dielectric material below a trigger voltage, and as a conductive material above the trigger voltage.

公开(公告)号：US20220093561A1

公开(公告)日：2022-03-24

申请号：US17025709

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel A. Elsherbini ,  Aleksandar Aleksov ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L23/00

Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.