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    MICROELECTRONIC ASSEMBLIES
    1.
    发明申请
    MICROELECTRONIC ASSEMBLIES 有权

    公开(公告)号：US20250022845A1

    公开(公告)日：2025-01-16

    申请号：US18827351

    申请日：2024-09-06

    Applicant: Intel Corporation

    Inventor： Adel A. Elsherbini ,  Feras Eid ,  Johanna M. Swan ,  Shawna M. Liff

    IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects.

    Microelectronic assemblies
    2.
    发明授权
    Microelectronic assemblies 有权

    公开(公告)号：US12199063B2

    公开(公告)日：2025-01-14

    申请号：US18403545

    申请日：2024-01-03

    Applicant: Intel Corporation

    Inventor： Shawna M. Liff ,  Adel A. Elsherbini ,  Johanna M. Swan ,  Arun Chandrasekhar

    IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

    Hermetic sealing structures in microelectronic assemblies having direct bonding
    3.
    发明授权
    Hermetic sealing structures in microelectronic assemblies having direct bonding 有权

    公开(公告)号：US12165962B2

    公开(公告)日：2024-12-10

    申请号：US17121093

    申请日：2020-12-14

    Applicant: Intel Corporation

    Inventor： Aleksandar Aleksov ,  Mohammad Enamul Kabir ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan ,  Feras Eid

    IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L23/48

    Abstract: Disclosed herein are microelectronic assemblies including microelectronic components coupled by direct bonding, and related structures and techniques. In some embodiments, a microelectronic assembly may include a first microelectronic component including a first guard ring extending through at least a portion of a thickness of and along a perimeter; a second microelectronic component including a second guard ring extending through at least a portion of a thickness of and along a perimeter, where the first and second microelectronic components are coupled by direct bonding; and a seal ring formed by coupling the first guard ring to the second guard ring. In some embodiments, a microelectronic assembly may include a microelectronic component coupled to an interposer that includes a first liner material at a first surface; a second liner material at an opposing second surface; and a perimeter wall through the interposer and connected to the first and second liner materials.

    MICROELECTRONIC ASSEMBLIES
    9.
    发明申请
    MICROELECTRONIC ASSEMBLIES 有权

    公开(公告)号：US20230127749A1

    公开(公告)日：2023-04-27

    申请号：US18086308

    申请日：2022-12-21

    Applicant: Intel Corporation

    Inventor： Shawna M. Liff ,  Adel A. Elsherbini ,  Johanna M. Swan ,  Arun Chandrasekhar

    IPC: H01L23/00 ,  H01L25/18 ,  H01L25/00

    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

    ACTIVE DEVICE LAYER AT INTERCONNECT INTERFACES
    10.
    发明申请
    ACTIVE DEVICE LAYER AT INTERCONNECT INTERFACES 有权

    公开(公告)号：US20220399324A1

    公开(公告)日：2022-12-15

    申请号：US17344348

    申请日：2021-06-10

    Applicant: Intel Corporation

    Inventor： Han Wui Then ,  Adel A. Elsherbini ,  Kimin Jun ,  Johanna M. Swan ,  Shawna M. Liff ,  Sathya Narasimman Tiagaraj ,  Gerald S. Pasdast ,  Aleksandar Aleksov ,  Feras Eid

    IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00

    Abstract: A die assembly comprising: a first component layer having conductive through-connections in an insulator, a second component layer comprising a die, and an active device layer (ADL) at an interface between the first component layer and the second component layer. The ADL comprises active elements electrically coupled to the first component layer and the second component layer. The die assembly further comprises a bonding layer electrically coupling the ADL to the second component layer. In some embodiments, the die assembly further comprises another ADL at another interface between the first component layer and a package support opposite to the interface. The first component layer may comprise another die having through-substrate vias (TSVs). The die and the another die may be fabricated using different process nodes.

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