LOW RESISTIVITY TUNGSTEN PVD WITH ENHANCED IONIZATION AND RF POWER COUPLING
    21.
    发明申请
    LOW RESISTIVITY TUNGSTEN PVD WITH ENHANCED IONIZATION AND RF POWER COUPLING 有权
    具有增强离子化和射频功率耦合的低电阻率TUNGSTEN PVD

    公开(公告)号:US20140042016A1

    公开(公告)日:2014-02-13

    申请号:US14054477

    申请日:2013-10-15

    Abstract: Embodiments described herein provide a semiconductor device and methods and apparatuses of forming the same. The semiconductor device includes a substrate having a source and drain region and a gate electrode stack on the substrate between the source and drain regions. In one embodiment, the method includes positioning a substrate within a processing chamber, wherein the substrate includes a source and drain region, a gate dielectric layer between the source and drain regions, and a conductive film layer on the gate dielectric layer. The method also includes depositing a refractory metal nitride film layer on the conductive film layer, depositing a silicon-containing film layer on the refractory metal nitride film layer, and depositing a tungsten film layer on the silicon-containing film layer.

    Abstract translation: 本文所述的实施例提供了一种半导体器件及其形成方法和装置。 半导体器件包括在源极和漏极区域之间的衬底上具有源极和漏极区域以及栅电极堆叠的衬底。 在一个实施例中,该方法包括将衬底定位在处理室内,其中衬底包括源极和漏极区域,源极和漏极区域之间的栅极介电层以及栅极电介质层上的导电膜层。 该方法还包括在导电膜层上沉积难熔金属氮化物膜层,在难熔金属氮化物膜层上沉积含硅膜层,并在含硅膜层上沉积钨膜层。

    METHOD FOR FORMATION OF CONFORMAL ALD SIO2 FILMS

    公开(公告)号:US20230416909A1

    公开(公告)日:2023-12-28

    申请号:US18336157

    申请日:2023-06-16

    CPC classification number: C23C16/402 C23C16/045

    Abstract: Embodiments of the disclosure provide a method of forming a dielectric film in trenches of a substrate. The utilization of the ALD process and introduction of an inhibitor material onto features defining the trenches and into the trenches provides for suppression of forming the dielectric film near the top surface of the features in the trenches. The dielectric film is formed via an ALD process. The ALD process includes sequentially exposing the substrate to an inhibitor material, a first precursor, a purge gas, an oxygen-containing precursor, and the purge gas during an ALD cycle, and repeating the ALD cycle to deposit the dielectric film.

    METHOD OF ENABLING SEAMLESS COBALT GAP-FILL
    26.
    发明申请

    公开(公告)号:US20170084486A1

    公开(公告)日:2017-03-23

    申请号:US15364780

    申请日:2016-11-30

    Abstract: Methods for depositing a metal layer in a feature definition of a semiconductor device are provided. In one implementation, a method for depositing a metal layer for forming a semiconductor device is provided. The method comprises performing a cyclic metal deposition process to deposit a metal layer on a substrate and annealing the metal layer disposed on the substrate. The cyclic metal deposition process comprises exposing the substrate to a deposition precursor gas mixture to deposit a portion of the metal layer on the substrate, exposing the portion of the metal layer to either a plasma treatment process or hydrogen annealing process and repeating the exposing the substrate to a deposition precursor gas mixture and exposing the portion of the metal layer to either a plasma treatment process or hydrogen annealing process until a predetermined thickness of the metal layer is achieved.

    METHOD FOR CLEANING TITANIUM ALLOY DEPOSITION
    27.
    发明申请
    METHOD FOR CLEANING TITANIUM ALLOY DEPOSITION 有权
    清洁钛合金沉积的方法

    公开(公告)号:US20150086722A1

    公开(公告)日:2015-03-26

    申请号:US14484423

    申请日:2014-09-12

    Abstract: Embodiments described herein relate to a thermal chlorine gas cleaning process. In one embodiment, a method for cleaning N-Metal film deposition in a processing chamber includes positioning a dummy substrate on a substrate support. The processing chamber is heated to at least about 50 degrees Celsius. The method further includes flowing chlorine gas into the processing chamber and evacuating chlorine gas from the processing chamber. In another embodiment, a method for cleaning titanium aluminide film deposition in a processing chamber includes heating the processing chamber to a temperature between about 70 about degrees Celsius and about 100 degrees Celsius, wherein the processing chamber and the substrate support include one or more fluid channels configured to heat or cool the processing chamber and the substrate support.

    Abstract translation: 本文所述的实施方案涉及热氯气清洗工艺。 在一个实施例中,用于清洁处理室中的N金属膜沉积的方法包括将虚设基板定位在基板支撑件上。 将处理室加热至至少约50摄氏度。 该方法还包括将氯气流入处理室并从处理室排出氯气。 在另一个实施方案中,一种用于清洁处理室中的铝化铝膜沉积的方法包括将处理室加热到约70摄氏度至约100摄氏度之间的温度,其中处理室和衬底支撑体包括一个或多个流体通道 被配置为加热或冷却处理室和基板支撑件。

    NMOS METAL GATE MATERIALS, MANUFACTURING METHODS, AND EQUIPMENT USING CVD AND ALD PROCESSES WITH METAL BASED PRECURSORS
    28.
    发明申请
    NMOS METAL GATE MATERIALS, MANUFACTURING METHODS, AND EQUIPMENT USING CVD AND ALD PROCESSES WITH METAL BASED PRECURSORS 有权
    NMOS金属栅材料,制造方法和使用基于金属的前驱体的CVD和ALD工艺的设备

    公开(公告)号:US20140120712A1

    公开(公告)日:2014-05-01

    申请号:US14147291

    申请日:2014-01-03

    Abstract: Embodiments provide methods for depositing metal-containing materials. The methods include deposition processes that form metal, metal carbide, metal silicide, metal nitride, and metal carbide derivatives by a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD. A method for processing a substrate is provided which includes depositing a dielectric material forming a feature definition in the dielectric material, depositing a work function material conformally on the sidewalls and bottom of the feature definition, and depositing a metal gate fill material on the work function material to fill the feature definition, wherein the work function material is deposited by reacting at least one metal-halide precursor having the formula MXY, wherein M is tantalum, hafnium, titanium, and lanthanum, X is a halide selected from the group of fluorine, chlorine, bromine, or iodine, and y is from 3 to 5.

    Abstract translation: 实施例提供了沉积含金属材料的方法。 所述方法包括通过包括热分解,CVD,脉冲CVD或ALD的气相沉积工艺形成金属,金属碳化物,金属硅化物,金属氮化物和金属碳化物衍生物的沉积工艺。 提供了一种用于处理衬底的方法,其包括在电介质材料中形成形成特征定义的电介质材料,将功函数材料保形地沉积在特征定义的侧壁和底部上,以及在工作功能上沉积金属栅极填充材料 用于填充特征定义的材料,其中通过使至少一种具有式MXY的金属卤化物前体与其中M是钽,铪,钛和镧的金属卤化物前体反应沉积功函材料,X是选自氟 ,氯,溴或碘,y为3至5。

    LOWERING TUNGSTEN RESISTIVITY BY REPLACING TITANIUM NITRIDE WITH TITANIUM SILICON NITRIDE
    29.
    发明申请
    LOWERING TUNGSTEN RESISTIVITY BY REPLACING TITANIUM NITRIDE WITH TITANIUM SILICON NITRIDE 审中-公开
    用硝酸钛替代硝酸钛降低电阻率

    公开(公告)号:US20140001576A1

    公开(公告)日:2014-01-02

    申请号:US13922063

    申请日:2013-06-19

    Abstract: Semiconductor devices, methods and apparatus for forming the same are provided. The semiconductor device includes a substrate having a source and drain region and a gate electrode stack on the substrate between the source and drain regions. The gate electrode stack includes a conductive film layer on a gate dielectric layer, a refractory metal silicon nitride film layer on the conductive film layer, and a tungsten film layer on the refractory metal silicon nitride film layer. In one embodiment, the method includes positioning a substrate within a processing chamber, wherein the substrate includes a source and drain region, a gate dielectric layer between the source and drain regions, and a conductive film layer on the gate dielectric layer. The method also includes depositing a refractory metal silicon nitride film layer on the conductive film layer and depositing a tungsten film layer on the refractory metal silicon nitride film layer.

    Abstract translation: 提供了用于形成半导体器件的方法和装置。 半导体器件包括在源极和漏极区域之间的衬底上具有源极和漏极区域以及栅电极堆叠的衬底。 栅极电极堆叠包括在栅极电介质层上的导电膜层,导电膜层上的难熔金属氮化硅膜层和难熔金属氮化硅膜层上的钨膜层。 在一个实施例中,该方法包括将衬底定位在处理室内,其中衬底包括源极和漏极区域,源极和漏极区域之间的栅极介电层以及栅极电介质层上的导电膜层。 该方法还包括在导电膜层上沉积难熔金属氮化硅膜层,并在难熔金属氮化硅膜层上沉积钨膜层。

    METHODS FOR PATTERNING SUBSTRATES TO ADJUST VOLTAGE PROPERTIES

    公开(公告)号:US20230377901A1

    公开(公告)日:2023-11-23

    申请号:US18139382

    申请日:2023-04-26

    CPC classification number: H01L21/3115 H01L21/31144 H01L21/31111

    Abstract: A method of forming a structure on a substrate is provided. The method includes depositing a dipole dopant containing (DDC) layer including a dipole dopant on a first and second region of a dielectric layer (DL) of the substrate. A hardmask (HM) is deposited over the DDC deposited on the first and the second regions. A patterned photoresist layer (PR) is formed over the HM. The PR includes a first portion that is positioned over the first region and an opening that is positioned to expose a portion of the HM that is disposed over the second region of the substrate. The HM and DDC within the second region are etched and at least a portion of the DL is exposed within the second region. The PR is removed and the substrate is annealed to diffuse the dipole dopant into a portion of the DL disposed in the first region.

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