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公开(公告)号：US20210099252A1
公开(公告)日：2021-04-01
申请号：US16933449
申请日：2020-07-20
Applicant: Apple Inc.
Inventor： Jafar Savoj , Praveen R. Singh , Brian S. Leibowitz , Emerson S. Fang
IPC: H04L1/02 , H03K19/0175
Abstract: A system and method for efficiently transporting data in a computing system are contemplated. In various embodiments, a computing system includes a source, a destination and multiple lanes between them for transporting data. Multiple receivers in the destination has a respective termination resistor connected to a single integrating capacitor, which provides a reference voltage to the multiple receivers. The receivers reconstruct the received data by comparing the corresponding input signals to the reference voltage. The source includes a table storing code words. The source maps a generated data word to a code word, which is sent to the destination. The destination maps the received code word to the data word. The values of the code words are selected to maintain a nearly same number of Boolean ones on the multiple lanes over time as a number of Boolean zeroes.
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公开(公告)号：US10756849B2
公开(公告)日：2020-08-25
申请号：US16253100
申请日：2019-01-21
Applicant: Apple Inc.
Inventor： Jafar Savoj , Praveen R. Singh , Brian S. Leibowitz , Emerson S. Fang
IPC: H04L1/02 , H03K19/0175 , H04L25/02 , H04L25/06 , H04L25/03
Abstract: A system and method for efficiently transporting data in a computing system are contemplated. In various embodiments, a computing system includes a source, a destination and multiple lanes between them for transporting data. Multiple receivers in the destination has a respective termination resistor connected to a single integrating capacitor, which provides a reference voltage to the multiple receivers. The receivers reconstruct the received data by comparing the corresponding input signals to the reference voltage. The source includes a table storing code words. The source maps a generated data word to a code word, which is sent to the destination. The destination maps the received code word to the data word. The values of the code words are selected to maintain a nearly same number of Boolean ones on the multiple lanes over time as a number of Boolean zeroes.
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公开(公告)号：US20200183874A1
公开(公告)日：2020-06-11
申请号：US16700356
申请日：2019-12-02
Applicant: Apple Inc.
Inventor： Jafar Savoj , Jose A. Tierno , Sanjeev K. Maheshwari , Brian S. Leibowitz , Pradeep R. Trivedi , Gin Yee , Emerson S. Fang
Abstract: A system and method for efficiently transporting data across lanes. A computing system includes an interconnect with lanes for transporting data between a source and a destination. When a source receives an indication of a bandwidth requirement change from a first data rate to a second data rate, the transmitter in the source sends messages to the receiver in the destination. The messages indicate that the data rate is going to change and reconfiguration of one or more lanes will be performed. The transmitter selects one or more lanes for transporting data at the second data rate. The transmitter maintains data transport at the first data rate while reconfiguring the selected one or more lanes to the second data rate. After completing the reconfiguration, the transmitter transports data at the second data rate on the selected one or more lanes while preventing data transport on any unselected lanes.
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公开(公告)号：US20190273503A1
公开(公告)日：2019-09-05
申请号：US16298803
申请日：2019-03-11
Applicant: Apple Inc.
Inventor： Brian S. Leibowitz , Jared L. Zerbe , Sanjay Pant
Abstract: Techniques are disclosed relating to rapidly downshifting the output frequency of an oscillator. In some embodiments, the oscillator is configured to operate in a closed-loop mode in which negative feedback is used to maintain a particular output frequency (e.g., in a phase-locked loop (PLL)). In some embodiments, the negative feedback loop is configured to maintain the output of the oscillator at a particular frequency based on a reference clock signal and the output of the oscillator. The nature of a negative feedback loop may render rapid frequency changes difficult, e.g., because of corrections by the loop. Therefore, in some embodiments, the loop is configured to switch to an open-loop mode in which a control input to the oscillator is fixed. In some embodiments, the loop switches to open-loop mode in response to a trigger signal and control circuitry forces the oscillator to a new target frequency.
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公开(公告)号：US20180083643A1
公开(公告)日：2018-03-22
申请号：US15419218
申请日：2017-01-30
Applicant: Apple Inc.
Inventor： Jared L. Zerbe , Brian S. Leibowitz , Sanjay Pant
IPC: H03L7/099 , G01R19/165
Abstract: Techniques are disclosed relating to detecting supply voltage events and performing corrective actions. In some embodiments, an apparatus includes sensor circuitry and control circuitry. In some embodiments, the sensor circuitry is configured to monitor supply voltage from a power supply and detect a load release event that includes an increase in the supply voltage that meets one or more pre-determined threshold parameters. In some embodiments, the control circuitry is configured to increase clock cycle time for operations performed by circuitry powered by the supply voltage during a time interval, wherein the time interval corresponds to ringing of the supply voltage that reduces the supply voltage and results from the load release event. In some embodiments, the disclosed techniques may reduce transients in supply voltage (which may avoid equipment damage and computing errors) and may allow for reduced voltage margins (which may reduce overall power consumption).
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Patent Agency Ranking
公开(公告)号：US20170089975A1
公开(公告)日：2017-03-30
申请号：US14868954
申请日：2015-09-29
Applicant: Apple Inc.
Inventor： Jafar Savoj , Brian S. Leibowitz , Emerson S. Fang
CPC classification number: G01R31/2874 , G01R31/2884 , G01R31/30 , G01R35/005 , G06F1/206 , G06F1/26 , G06F1/3203 , H03K19/003
Abstract: An apparatus and method for performing on-chip parameter measurement is disclosed. In one embodiment, an IC includes a number of functional circuit blocks each having one or more sensors for measuring parameters such as voltage and temperature. Each of the functional blocks includes circuitry coupled to receive power from a local supply voltage node. Similarly, the circuitry in each of the sensors is also coupled to receive power from the corresponding local supply voltage node. Each of the sensors may be calibrated to compensate for process, voltage, and temperature variations. Various methods based on characterization of the sensors may be used to perform the calibrations.
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公开(公告)号：US11757681B1
公开(公告)日：2023-09-12
申请号：US17934891
申请日：2022-09-23
Applicant: Apple Inc.
Inventor： Jose A. Tierno , Haiming Jin , Brian S. Leibowitz , Sanjeev K. Maheshwari , Chintan S. Thakkar
IPC: H04L25/03
CPC classification number: H04L25/03057 , H04L25/03885
Abstract: To compensate for intersymbol interference, a serial data receiver circuit included in a computer system may include an equalizer circuit that includes a digital-to-analog converter circuit. Based on previously received symbols, the equalizer circuit modifies a signal received via a communication channel or link prior to clock and data recovery. In cases when the digital-to-analog converter circuit becomes saturated, the equalizer circuit additionally uses a dither signal to modify the received signal.
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公开(公告)号：US11658671B2
公开(公告)日：2023-05-23
申请号：US17482322
申请日：2021-09-22
Applicant: Apple Inc.
Inventor： Ryan D. Bartling , Jafar Savoj , Brian S. Leibowitz , Shah M. Sharif
CPC classification number: H03M1/0687 , H03M1/0626 , H03M1/0648 , H03M1/0663
Abstract: A serial data receiver circuit included in a computer system may include a front-end circuit, a sample circuit that includes multiple analog-to-digital converter circuits, and a recovery circuit. The front-end circuit may generate an equalized signal using multiple signals that encode a serial data stream of multiple data symbols. Based on a baud rate of the serial data stream, a determined number of the multiple analog-to-digital converter circuits sample, using a recovered clock signal, the equalized signal at the respective times to generate corresponding samples. The recovery circuit generates, using the samples, the recovered clock signal and recovered data symbols.
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公开(公告)号：US11502880B1
公开(公告)日：2022-11-15
申请号：US17478069
申请日：2021-09-17
Applicant: Apple Inc.
Inventor： Ryan D. Bartling , Jafar Savoj , Brian S. Leibowitz
Abstract: A receiver converter circuit included in a computer system may receive multiple signals that encode a serial data stream that encode multiple data symbols. To correct for baseline wander, the receiver circuit may generate a disparity signal that is used to control the application of a differential voltage to the multiple signals. The receiver circuit may also employ the disparity signal to generate a gradient against which the magnitude of differential voltage is calibrated.
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公开(公告)号：US20220140833A1
公开(公告)日：2022-05-05
申请号：US17455338
申请日：2021-11-17
Applicant: Apple Inc.
Inventor： Jared L. Zerbe , Brian S. Leibowitz , Sanjay Pant
Abstract: Techniques are disclosed relating to detecting supply voltage events and performing corrective actions. In some embodiments, an apparatus includes sensor circuitry and control circuitry. In some embodiments, the sensor circuitry is configured to monitor supply voltage from a power supply and detect a load release event that includes an increase in the supply voltage that meets one or more pre-determined threshold parameters. In some embodiments, the control circuitry is configured to increase clock cycle time for operations performed by circuitry powered by the supply voltage during a time interval, wherein the time interval corresponds to ringing of the supply voltage that reduces the supply voltage and results from the load release event. In some embodiments, the disclosed techniques may reduce transients in supply voltage (which may avoid equipment damage and computing errors) and may allow for reduced voltage margins (which may reduce overall power consumption).
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