公开(公告)号：US20190035623A1

公开(公告)日：2019-01-31

申请号：US16148430

申请日：2018-10-01

Applicant: Applied Materials, Inc.

Inventor： Chun YAN ,  Xinyu BAO ,  Melitta Manyin HON ,  Hua CHUNG ,  Schubert S. CHU

IPC: H01L21/02 ,  H01L29/66

Abstract: Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices. Benefits of this disclosure include precise fin size control in devices, such as 10 nm FinFET devices, and increased overall device yield. The method of integrated clean and recess includes establishing a low pressure processing environment in the processing volume, and maintaining the low pressure processing environment while flowing a first gas over a substrate in a processing volume, depositing a salt on the substrate, heating the processing volume to greater than 90° C., purging the processing volume with a second inert gas, and recessing a source/drain region disposed on the substrate.

公开(公告)号：US20180286962A1

公开(公告)日：2018-10-04

申请号：US15926921

申请日：2018-03-20

Applicant: Applied Materials, Inc.

Inventor： Xinyu BAO ,  Zhiyuan YE ,  Hua CHUNG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/167 ,  H01L29/08

CPC classification number: H01L29/6659 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7851

Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.

公开(公告)号：US20180230624A1

公开(公告)日：2018-08-16

申请号：US15889669

申请日：2018-02-06

Applicant: Applied Materials, Inc.

Inventor： Abhishek DUBE ,  Xuebin LI ,  Hua CHUNG ,  Flora Fong-Song CHANG

IPC: C30B25/18 ,  C30B29/06 ,  C30B33/12 ,  C23C16/02 ,  C23C16/56 ,  H01L21/67 ,  H01L21/02 ,  H01L21/3065

Abstract: The present disclosure generally relate to a cluster tool and methods for forming an epitaxial layer on a semiconductor device. In one implementation, the cluster tool includes a transfer chamber, a pre-clean chamber coupled to the transfer chamber, a plasma-cleaning chamber coupled to the transfer chamber, a deposition chamber coupled to the transfer chamber, an etch chamber coupled to the transfer chamber, and a thermal process chamber coupled to the transfer chamber.

公开(公告)号：US20180083104A1

公开(公告)日：2018-03-22

申请号：US15418286

申请日：2017-01-27

Applicant: Applied Materials, Inc.

Inventor： Yi-Chiau HUANG ,  Hua CHUNG ,  Sheng-Chin KUNG ,  Xuebin LI

IPC: H01L29/167 ,  H01L29/161 ,  H01L21/225 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/02

CPC classification number: H01L29/167 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02656 ,  H01L21/02661 ,  H01L21/02667 ,  H01L21/2018 ,  H01L21/2033 ,  H01L21/2053 ,  H01L21/2252 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/67184 ,  H01L21/67207 ,  H01L29/161 ,  H01L29/785

Abstract: Implementations described herein generally relate to methods and systems for depositing layer on substrates, and more specifically, to methods for forming boron or gallium-doped germanium on silicon-containing surfaces. In one implementation, a method of processing a substrate is provided. The method comprises exposing a substrate having an exposed silicon-germanium surface and an exposed dielectric surface to a pre-treatment process, selectively depositing a boron-doped or a gallium-doped layer on the exposed silicon-germanium surface and exposing the substrate to a post-treatment process.

公开(公告)号：US20180082874A1

公开(公告)日：2018-03-22

申请号：US15267232

申请日：2016-09-16

Applicant: Applied Materials, Inc.

Inventor： Xinyu BAO ,  Chun YAN ,  Hua CHUNG ,  Schubert S. CHU

IPC: H01L21/673

CPC classification number: H01L21/67 ,  H01L21/673 ,  H01L21/67393 ,  H01L21/677

Abstract: Embodiments disclosed herein generally relate to apparatus and methods for controlling substrate outgassing such that hazardous gasses are eliminated from a surface of a substrate after a Si:As process has been performed on a substrate, and prior to additional processing. The apparatus includes a purge station including an enclosure, a gas supply coupled to the enclosure, an exhaust pump coupled to the enclosure, a first purge gas port formed in the enclosure, a first channel operatively connected to the gas supply at a first end and to the first purge gas port at a second end, a second purge gas port formed in the enclosure, and a second channel operatively connected to the second purge gas port at a third end and to the exhaust pump at a fourth end. The first channel includes a particle filter, a heater, and a flow controller. The second channel includes a dry scrubber.

公开(公告)号：US20170323795A1

公开(公告)日：2017-11-09

申请号：US15585016

申请日：2017-05-02

Applicant: Applied Materials, Inc.

Inventor： Xuebin LI ,  Hua CHUNG ,  Flora Fong-Song CHANG ,  Abhishek DUBE ,  Yi-Chiau HUANG ,  Schubert S. CHU

IPC: H01L21/3065 ,  H01L29/66 ,  H01L29/08 ,  H01L21/67

CPC classification number: H01L21/3065 ,  H01L21/67069 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7836 ,  H01L29/7848

Abstract: Methods for forming transistors are provided. A substrate is placed in a processing chamber, and a plurality of epitaxial features is formed on the substrate. The epitaxial feature has at least a surface having the (110) plane and a surface having the (100) plane. An etchant or a gas mixture including an etchant and an etch enhancer or an etch suppressor is introduced into the processing chamber to remove a portion of the epitaxial feature. Etch selectivity between the surface having the (110) plane and the surface having the (100) plane can be tuned by varying the pressure within the processing chamber, the ratio of the flow rate of the etchant or gas mixture to the flow rate of a carrier gas, and/or the ratio of the flow rate of the etch enhancer or suppressor to the flow rate of the etchant.

公开(公告)号：US20150118822A1

公开(公告)日：2015-04-30

申请号：US14068312

申请日：2013-10-31

Applicant: APPLIED MATERIALS, INC.

Inventor： Ying ZHANG ,  Hua CHUNG ,  Srinivas D. NEMANI ,  Ludovic GODET

IPC: H01L21/762 ,  H01L21/265

CPC classification number: H01L21/76224 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/6831 ,  H01L29/66795

Abstract: Embodiments of the present invention provide a methods for forming silicon recess structures in a substrate with good process control, particularly suitable for manufacturing three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of forming recess structures in a substrate includes etching a first portion of a substrate defined by a second portion formed in the substrate until a doping layer formed in the substrate is exposed.

Abstract translation: 本发明的实施例提供了一种用于在具有良好的工艺控制的衬底中形成硅凹陷结构的方法，特别适用于制造用于半导体芯片的鳍式场效应晶体管（FinFET）的三维（3D）堆叠。 在一个实施例中，在衬底中形成凹陷结构的方法包括蚀刻由形成在衬底中的第二部分限定的衬底的第一部分，直到形成在衬底中的掺杂层露出。

公开(公告)号：US20240218503A1

公开(公告)日：2024-07-04

申请号：US18608005

申请日：2024-03-18

Applicant: Applied Materials, Inc.

Inventor： Sang-Ho YU ,  Kevin MORAES ,  Seshadri GANGULI ,  Hua CHUNG ,  See-Eng PHAN

IPC: C23C16/16 ,  C23C16/02 ,  C23C16/18 ,  C23C16/455 ,  C23C16/50 ,  H01L21/02 ,  H01L21/285 ,  H01L21/324 ,  H01L21/768

CPC classification number: C23C16/16 ,  C23C16/0218 ,  C23C16/0245 ,  C23C16/18 ,  C23C16/4554 ,  C23C16/45542 ,  C23C16/50 ,  H01L21/02068 ,  H01L21/02074 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/324 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76862 ,  H01L21/76883

Abstract: Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface. In another embodiment, a deposition-treatment cycle includes performing the vapor deposition process and subsequently a post-treatment process, which deposition-treatment cycle may be repeated to form multiple cobalt capping layers.

公开(公告)号：US20180076324A1

公开(公告)日：2018-03-15

申请号：US15414080

申请日：2017-01-24

Applicant: Applied Materials, Inc.

Inventor： Yi-Chiau HUANG ,  Hua CHUNG ,  Xuebin LI

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7839 ,  H01L21/28512 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/66628 ,  H01L29/66643

Abstract: Implementations of the present disclosure generally relate to improved semiconductor devices and methods of manufacture thereof. More specifically, implementations disclosed herein relate to a semiconductor device having an improved contact interface between the semiconductor material and metal material and methods of manufacture thereof. The method includes forming a semiconductor layer on a silicon substrate, forming an interfacial layer over the semiconductor layer, and forming a metal contact layer over the interfacial layer. The interfacial layer comprises one or more of germanium, boron, gallium, indium, thallium, arsenic, antimony, tin, silicon, and phosphorus, and has a thickness of between about 50 angstroms and about 100 angstroms. The interfacial layer improves the quality of the contact interface between the semiconductor material and metal material.

公开(公告)号：US20180076065A1

公开(公告)日：2018-03-15

申请号：US15418506

申请日：2017-01-27

Applicant: Applied Materials, Inc.

Inventor： Xinyu BAO ,  Hua CHUNG ,  Schubert S. CHU

IPC: H01L21/67 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/285 ,  H01J37/32 ,  C30B25/04 ,  C30B25/18 ,  C30B29/06 ,  B08B7/00

CPC classification number: H01L21/67207 ,  B08B7/0035 ,  C30B25/04 ,  C30B25/186 ,  C30B29/06 ,  H01J37/32458 ,  H01J37/32899 ,  H01J2237/334 ,  H01L21/02046 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/3065 ,  H01L21/67167 ,  H01L21/67184 ,  H01L21/67201 ,  H01L29/66636 ,  H01L29/66795

Abstract: Implementations of the present disclosure generally relate to methods and apparatuses for epitaxial deposition on substrate surfaces. More particularly, implementations of the present disclosure generally relate to an integrated system for processing N-type metal-oxide semiconductor (NMOS) devices. In one implementation, a cluster tool for processing a substrate is provided. The cluster tool includes a pre-clean chamber, an etch chamber, one or more pass through chambers, one or more outgassing chambers, a first transfer chamber, a second transfer chamber, and one or more process chambers. The pre-clean chamber and the etch chamber are coupled to a first transfer chamber. The one or more pass through chambers are coupled to and disposed between the first transfer chamber and the second transfer chamber. The one or more outgassing chambers are coupled to the second transfer chamber. The one or more process chambers are coupled to the second transfer chamber.