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    SEMICONDUCTOR DEVICES
    214.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20240379366A1

    公开(公告)日：2024-11-14

    申请号：US18779268

    申请日：2024-07-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuei-Lun Lin ,  Chia-Wei Hsu ,  Xiong-Fei Yu ,  Chi On Chui ,  Chih-Yu Hsu ,  Jian-Hao Chen

    IPC: H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/66

    Abstract: In an embodiment, a method includes: depositing a gate dielectric layer on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction, a distance between the first fin and the second fin decreasing along the first direction; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer; annealing the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer.

    TRANSISTOR GATE CONTACTS
    216.
    发明申请
    TRANSISTOR GATE CONTACTS 有权

    公开(公告)号：US20240371689A1

    公开(公告)日：2024-11-07

    申请号：US18777293

    申请日：2024-07-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Chi On Chui

    IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/417 ,  H01L29/66

    Abstract: In an embodiment, a device includes: a source/drain region adjoining a channel region of a substrate; a contact etch stop layer on the source/drain region; a first source/drain contact extending through the contact etch stop layer, the first source/drain contact connected to the source/drain region; a gate structure on the channel region; a gate contact connected to the gate structure; and a contact spacer around the gate contact, where the contact spacer, the gate structure, the contact etch stop layer, and the substrate collectively define a void between the gate structure and the first source/drain contact.

    Three-Dimensional Memory Device with Ferroelectric Material
    217.
    发明公开
    Three-Dimensional Memory Device with Ferroelectric Material 审中-公开

    公开(公告)号：US20240365553A1

    公开(公告)日：2024-10-31

    申请号：US18763593

    申请日：2024-07-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chi On Chui ,  Han-Jong Chia ,  Chenchen Jacob Wang

    IPC: H10B51/20 ,  H10B51/10 ,  H10B51/30

    CPC classification number: H10B51/20 ,  H10B51/10 ,  H10B51/30

    Abstract: A method of forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, the first layer stack and the second layer stack having a same layered structure that includes a dielectric material, a channel material over the dielectric material, and a source/drain material over the channel material; forming openings that extend through the first layer stack and the second layer stack; forming inner spacers by replacing portions of the source/drain material exposed by the openings with a first dielectric material; lining sidewalls of the openings with a ferroelectric material; forming gate electrodes by filling the openings with an electrically conductive material; forming a recess through the first layer stack and the second layer stack, the recess extending from a sidewall of the second layer stack toward the gate electrodes; and filling the recess with a second dielectric material.

    Work function control in gate structures
    218.
    发明授权
    Work function control in gate structures 有权

    公开(公告)号：US12132112B2

    公开(公告)日：2024-10-29

    申请号：US17875561

    申请日：2022-07-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

    Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Ji-Cheng Chen ,  Weng Chang ,  Chi On Chui

    IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

    CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

    Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a nanostructured channel region disposed on the fin structure, and a gate-all-around (GAA) structure surrounding the nanostructured channel region. The GAA structure includes a high-K (HK) gate dielectric layer with a metal doped region having dopants of a first metallic material, a p-type work function metal (pWFM) layer disposed on the HK gate dielectric layer, a bimetallic nitride layer interposed between the HK gate dielectric layer and the pWFM layer, an n-type work function metal (nWFM) layer disposed on the pWFM layer, and a gate metal fill layer disposed on the nWFM layer. The pWFM layer includes a second metallic material and the bimetallic nitride layer includes the first and second metallic materials.

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