公开(公告)号：US11963466B2

公开(公告)日：2024-04-16

申请号：US17330610

申请日：2021-05-26

Applicant: Infineon Technologies AG

Inventor： Dominik Heiss ,  Christoph Kadow ,  Matthias Markert

IPC: H10N70/20 ,  H10N70/00

CPC classification number: H10N70/253 ,  H10N70/066 ,  H10N70/823 ,  H10N70/8265 ,  H10N70/8613 ,  H10N70/231 ,  H10N70/8616 ,  H10N70/8828

Abstract: A switch device including a semiconductor substrate is provided. A trench is formed in the substrate, and a phase change material is provided at least partially in the trench. A heater for heating the phase change material is also provided.

公开(公告)号：US20240099165A1

公开(公告)日：2024-03-21

申请号：US18154959

申请日：2023-01-16

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHINOLOGY ,  RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY

Inventor： Heejun YANG ,  Eunji Hwang ,  Yonas Assefa Eshete

IPC: H10N70/20 ,  H10N70/00

CPC classification number: H10N70/253 ,  H10N70/235 ,  H10N70/8828

Abstract: Provided is a semiconductor device. The semiconductor device includes a phase change material layer on a substrate, a gate electrode disposed on the phase change material layer and inducing accumulation of charges in the phase change material layer, and a pair of source/drain electrodes spaced apart from each other with the gate electrode therebetween on the phase change material layer. The phase change material layer includes a phase change region having a crystal structure that changes due to the accumulation of the charges as a voltage is applied to the gate electrode.

公开(公告)号：US11889775B2

公开(公告)日：2024-01-30

申请号：US16770662

申请日：2018-12-17

Applicant: NORTHWESTERN UNIVERSITY

Inventor： Vinod K. Sangwan ,  Hong-Sub Lee ,  Mark C. Hersam

IPC: H10N70/20 ,  G11C13/00 ,  H10B63/00 ,  H10N70/00 ,  G06N3/049 ,  G06N3/088 ,  G06N3/065

CPC classification number: H10N70/253 ,  G11C13/0002 ,  H10B63/30 ,  H10N70/023 ,  H10N70/24 ,  H10N70/823 ,  H10N70/841 ,  H10N70/8822 ,  H10N70/8825 ,  G06N3/049 ,  G06N3/065 ,  G06N3/088

Abstract: One aspect of the invention relates to a multi-terminal memtransistor. The memtransistor includes a substrate having a first surface and an opposite, second surface, a polycrystalline monolayer film formed of an atomically thin material on the first surface of the substrate, an electrode array having a plurality of electrodes spatial-apart formed on the polycrystalline monolayer film such that each pair of electrodes defines a channel in the polycrystalline monolayer film therebetween, and a gate electrode formed on the second surface of the substrate and capacitively coupled with the channel. The polycrystalline monolayer film contains grains defining a plurality of grain boundaries thereof. The multi-terminal memtransistor operates much like a neuron by performing both memory and information processing, and can be a foundational circuit element for new forms of neuromorphic computing.

公开(公告)号：US11812676B2

公开(公告)日：2023-11-07

申请号：US16828242

申请日：2020-03-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy Mathew Philip ,  Lawrence A. Clevenger ,  Kevin W. Brew

IPC: H10N70/20 ,  H10N70/00

CPC classification number: H10N70/861 ,  H10N70/011 ,  H10N70/231 ,  H10N70/253 ,  H10N70/823 ,  H10N70/826 ,  H10N70/8413 ,  H10N70/883 ,  H10N70/8828

Abstract: A phase change memory device is provided. The phase change memory device includes a phase change memory material within an electrically insulating wall, a first heater terminal in the electrically insulating wall, and two read terminals in the electrically insulating wall.

公开(公告)号：US11793003B2

公开(公告)日：2023-10-17

申请号：US16926239

申请日：2020-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huang-Kui Chen ,  Guan-Jie Shen

IPC: H01L23/528 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/34 ,  H01L23/528 ,  H10N70/021 ,  H10N70/253

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure, a conductor layer over and in contact with the layer of dielectric material and above the S/D contact structure, and an interconnect structure over and in contact with the conductor layer.

公开(公告)号：US11758740B2

公开(公告)日：2023-09-12

申请号：US17224152

申请日：2021-04-07

Applicant: Winbond Electronics Corp.

Inventor： Chang-Tsung Pai ,  Chiung-Lin Hsu ,  Yu-Ting Chen ,  Ming-Che Lin ,  Chi-Ching Liu

IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/30 ,  H10N70/011 ,  H10N70/253 ,  H10N70/8265 ,  H10N70/841

Abstract: A three-dimensional semiconductor device includes multiple semiconductor device layers on a substrate, wherein each layer includes a first stacked structure, a first gate dielectric layer, a first semiconductor layer, a first channel layer, a first source region, a first drain region, and a first resistive random access memory cell. The first stacked structure on the substrate includes a first insulating layer and a first gate conductor layer. The first gate dielectric layer surrounds a sidewall of the first stacked structure. The first semiconductor layer surrounds a sidewall of the first gate dielectric layer. The first channel layer is in the first semiconductor layer. The first source region and the first drain region are on both sides of the first channel layer in the first semiconductor layer. The first resistive random access memory cell is on a first sidewall of the first semiconductor layer and connected to the first drain region.

公开(公告)号：US20230253040A1

公开(公告)日：2023-08-10

申请号：US18301745

申请日：2023-04-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Der Chih ,  Jonathan Tsung-Yung Chang ,  Yun-Sheng Chen ,  May-Be Chen ,  Ya-Chin King ,  Wen Zhang Lin ,  Chrong Lin ,  Hsin-Yuan Yu

IPC: G11C13/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: G11C13/004 ,  G11C13/0069 ,  H10B63/30 ,  H10N70/253 ,  G11C2013/0045 ,  G11C2013/0078

Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.

公开(公告)号：US11723292B2

公开(公告)日：2023-08-08

申请号：US16910609

申请日：2020-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yang Chang ,  Wen-Ting Chu ,  Kuo-Chi Tu ,  Yu-Wen Liao ,  Hsia-Wei Chen ,  Chin-Chieh Yang ,  Sheng-Hung Shih ,  Wen-Chun You

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/8265 ,  H10B63/30 ,  H10N70/011 ,  H10N70/063 ,  H10N70/066 ,  H10N70/20 ,  H10N70/24 ,  H10N70/826 ,  H10N70/841 ,  H10N70/8833 ,  H10N70/021 ,  H10N70/023 ,  H10N70/026 ,  H10N70/028 ,  H10N70/041 ,  H10N70/043 ,  H10N70/046 ,  H10N70/061 ,  H10N70/068 ,  H10N70/231 ,  H10N70/235 ,  H10N70/245 ,  H10N70/25 ,  H10N70/253 ,  H10N70/257 ,  H10N70/801 ,  H10N70/821 ,  H10N70/823 ,  H10N70/828 ,  H10N70/8413 ,  H10N70/8416 ,  H10N70/8418 ,  H10N70/8613 ,  H10N70/8616 ,  H10N70/881 ,  H10N70/882 ,  H10N70/883 ,  H10N70/884 ,  H10N70/8822 ,  H10N70/8825 ,  H10N70/8828 ,  H10N70/8836 ,  H10N70/8845

Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.

公开(公告)号：US20230200264A1

公开(公告)日：2023-06-22

申请号：US18172762

申请日：2023-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Miao Liu ,  Bwo-Ning Chen ,  Kei-Wei Chen

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/063 ,  H10N70/231 ,  H10N70/253

Abstract: A method of forming a semiconductor device includes patterning a mask layer and a semiconductor material to form a first fin and a second fin with a trench interposing the first fin and the second fin. A first liner layer is formed over the first fin, the second fin, and the trench. An insulation material is formed over the first liner layer. A first anneal is performed, followed by a first planarization of the insulation material to form a first planarized insulation material. After which, a top surface of the first planarized insulation material is over a top surface of the mask layer. A second anneal is performed, followed by a second planarization of the first planarized insulation material to form a second planarized insulation material. The insulation material is etched to form shallow trench isolation (STI) regions, and a gate structure is formed over the semiconductor material.

公开(公告)号：US12125895B2

公开(公告)日：2024-10-22

申请号：US16915600

申请日：2020-06-29

Applicant: Intel Corporation

Inventor： Chelsey Dorow ,  Kevin O'Brien ,  Carl Naylor ,  Uygar Avci ,  Sudarat Lee ,  Ashish Verma Penumatcha ,  Chia-Ching Lin ,  Tanay Gosavi ,  Shriram Shivaraman ,  Kirby Maxey

IPC: H01L29/66 ,  B82Y10/00 ,  B82Y25/00 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H10B63/00 ,  H10N70/20

CPC classification number: H01L29/66439 ,  H01L21/02568 ,  H01L29/66969 ,  H01L29/775 ,  H01L29/78696 ,  H10B63/30 ,  H10B63/34 ,  H10N70/253

Abstract: A transistor includes a channel including a first layer including a first monocrystalline transition metal dichalcogenide (TMD) material, where the first layer is stoichiometric and includes a first transition metal. The channel further includes a second layer above the first layer, the second layer including a second monocrystalline TMD material, where the second monocrystalline TMD material includes a second transition metal and oxygen, and where the second layer is sub-stoichiometric. The transistor further includes a gate electrode above a first portion of the channel layer, a gate dielectric layer between the channel layer and the gate electrode, a source contact on a second portion of the channel layer and a drain contact on a third portion of the channel layer, where the gate electrode is between drain contact and the source contact.