公开(公告)号：US11853867B2

公开(公告)日：2023-12-26

申请号：US17504784

申请日：2021-10-19

Applicant: Cerebras Systems Inc.

Inventor： Sean Lie ,  Michael Morrison ,  Srikanth Arekapudi ,  Michael Edwin James ,  Gary R. Lauterbach

IPC: G06N3/063 ,  G06N3/08 ,  G06F9/30 ,  G06F5/06 ,  G06F13/40 ,  G06N3/04 ,  G06N3/047 ,  G06N3/048 ,  G06F13/00 ,  G06N3/084 ,  H04L49/00 ,  G06F9/38 ,  H04L12/54 ,  G06N3/044 ,  G06N3/045 ,  H04L49/506 ,  G06F30/392

CPC classification number: G06N3/063 ,  G06F5/06 ,  G06F9/3001 ,  G06F9/3009 ,  G06F9/30014 ,  G06F9/3016 ,  G06F9/30036 ,  G06F9/30087 ,  G06F9/30192 ,  G06F9/3851 ,  G06F13/00 ,  G06F13/4027 ,  G06N3/04 ,  G06N3/044 ,  G06N3/045 ,  G06N3/047 ,  G06N3/048 ,  G06N3/08 ,  G06N3/084 ,  H04L12/56 ,  H04L49/3018 ,  G06F30/392 ,  H04L49/3045 ,  H04L49/506

Abstract: Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements performs flow-based computations on wavelets of data. Each processing element has a compute element and a routing element. Each router enables communication via wavelets with at least nearest neighbors in a 2D mesh. Routing is controlled by virtual channel specifiers in each wavelet and routing configuration information in each router. Execution of an activate instruction or completion of a fabric vector operation activates one of the virtual channels. A virtual channel is selected from a pool comprising previously activated virtual channels and virtual channels associated with previously received wavelets. A task corresponding to the selected virtual channel is activated by executing instructions corresponding to the selected virtual channel.

公开(公告)号：US20230396533A1

公开(公告)日：2023-12-07

申请号：US18454860

申请日：2023-08-24

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Jonathan P. Beecroft

IPC: H04L45/28 ,  H04L45/028 ,  H04L45/125 ,  H04L45/00 ,  H04L45/122 ,  H04L47/76 ,  H04L49/15 ,  H04L49/00 ,  H04L69/40 ,  H04L47/10 ,  H04L49/9005 ,  H04L47/34 ,  H04L67/1097 ,  G06F13/16 ,  H04L45/021 ,  H04L47/12 ,  G06F13/42 ,  H04L47/2441 ,  H04L47/30 ,  H04L47/62 ,  H04L47/24 ,  H04L49/90 ,  G06F13/38 ,  G06F13/40 ,  H04L45/745 ,  H04L47/2483 ,  H04L47/629 ,  H04L47/80 ,  H04L49/101 ,  H04L45/12 ,  H04L47/122 ,  G06F12/1036 ,  G06F15/173 ,  H04L43/10 ,  H04L45/42 ,  H04L47/11 ,  G06F12/0862 ,  G06F12/1045 ,  H04L47/32 ,  G06F9/54 ,  G06F13/14 ,  G06F9/50 ,  H04L47/22 ,  H04L47/52 ,  H04L47/6275 ,  H04L45/24 ,  H04L45/7453 ,  H04L45/16 ,  H04L69/22 ,  H04L47/762 ,  H04L47/78 ,  H04L47/20 ,  H04L49/9047 ,  H04L1/00 ,  H04L43/0876 ,  H04L47/2466 ,  H04L47/625

CPC classification number: H04L45/28 ,  H04L45/028 ,  H04L45/125 ,  H04L45/22 ,  H04L45/122 ,  H04L47/76 ,  H04L49/15 ,  H04L49/30 ,  H04L69/40 ,  H04L47/39 ,  H04L49/9005 ,  H04L47/34 ,  H04L67/1097 ,  G06F13/1673 ,  G06F13/1689 ,  H04L45/021 ,  H04L45/38 ,  H04L47/12 ,  G06F13/1642 ,  G06F13/4221 ,  H04L47/2441 ,  H04L47/30 ,  H04L47/621 ,  H04L47/24 ,  H04L49/9021 ,  G06F13/16 ,  G06F13/385 ,  G06F13/4022 ,  H04L45/745 ,  H04L47/2483 ,  H04L47/629 ,  H04L47/80 ,  H04L49/101 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/3027 ,  H04L45/123 ,  H04L47/122 ,  H04L45/566 ,  G06F12/1036 ,  G06F15/17331 ,  H04L49/90 ,  H04L43/10 ,  H04L45/20 ,  H04L45/42 ,  H04L47/11 ,  H04L47/18 ,  G06F12/0862 ,  G06F12/1063 ,  H04L47/323 ,  G06F9/546 ,  G06F13/14 ,  G06F9/505 ,  H04L47/22 ,  H04L47/52 ,  H04L47/6275 ,  H04L45/24 ,  H04L45/7453 ,  H04L45/16 ,  H04L69/22 ,  G06F13/4068 ,  H04L47/6235 ,  H04L47/762 ,  H04L47/781 ,  H04L47/20 ,  H04L49/9036 ,  H04L49/9047 ,  H04L1/0083 ,  H04L43/0876 ,  H04L45/46 ,  H04L45/70 ,  H04L47/2466 ,  H04L47/626 ,  H04L47/32 ,  G06F2213/0026 ,  G06F2213/3808 ,  G06F2212/50 ,  H04L69/28

Abstract: Data-driven intelligent networking systems and methods are provided. The system can accommodate dynamic traffic with fast, effective congestion control. The system can maintain state information of individual packet flows, which can be set up or released dynamically based on injected data. Each flow can be provided with a flow-specific input queue upon arriving at a switch. Packets of a respective flow can be acknowledged after reaching the egress point of the network, and the acknowledgement packets can be sent back to the ingress point of the flow along the same data path. As a result, each switch can obtain state information of each flow and perform flow control on a per-flow basis.

公开(公告)号：US11811672B2

公开(公告)日：2023-11-07

申请号：US17825060

申请日：2022-05-26

Applicant: Airbus (S.A.S.)

Inventor： Markus Klügel ,  Paulo Mendes

IPC: H04L47/56 ,  H04L49/00

CPC classification number: H04L47/56 ,  H04L49/3018

Abstract: Systems and methods for data scheduling and queuing. A data network node is configured to transmit data in a store-and-forward fashion. The data network node includes a delay and validity determination module that determines and assigns a validity value to each data packet incoming via an input port based on a time stamp of the data packet, a current time value, an expected delay on a route of the data packet to its destination, and a packet urgency value. A scheduling module and a queue managing module execute their functions based on the validity value assigned to a data packet in a transmission buffer.

公开(公告)号：US11770463B2

公开(公告)日：2023-09-26

申请号：US17236830

申请日：2021-04-21

Applicant: VIAVI SOLUTIONS INC.

Inventor： Sherwood Johnson

IPC: H04L69/22 ,  H04L45/745 ,  H04L49/00 ,  H04L49/9047 ,  H04L49/90

CPC classification number: H04L69/22 ,  H04L45/745 ,  H04L49/3018 ,  H04L49/9036 ,  H04L49/9047

Abstract: A packet filtering system uses linked zero-based binary search trees to filter received packets. The binary search trees may be generated from filter conditions defining filter parameters for filtering packets.

公开(公告)号：US11757763B2

公开(公告)日：2023-09-12

申请号：US17594647

申请日：2020-03-23

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Igor Gorodetsky ,  Hess M. Hodge ,  Timothy J. Johnson

IPC: G06F13/42 ,  H04L45/28 ,  H04L45/028 ,  H04L45/125 ,  H04L45/00 ,  H04L45/122 ,  H04L47/76 ,  H04L49/15 ,  H04L49/00 ,  H04L69/40 ,  H04L47/10 ,  H04L49/9005 ,  H04L47/34 ,  H04L67/1097 ,  G06F13/16 ,  H04L45/021 ,  H04L47/12 ,  H04L47/2441 ,  H04L47/30 ,  H04L47/62 ,  H04L47/24 ,  H04L49/90 ,  G06F13/38 ,  G06F13/40 ,  H04L45/745 ,  H04L47/2483 ,  H04L47/629 ,  H04L47/80 ,  H04L49/101 ,  H04L45/12 ,  H04L47/122 ,  G06F12/1036 ,  G06F15/173 ,  H04L43/10 ,  H04L45/42 ,  H04L47/11 ,  G06F12/0862 ,  G06F12/1045 ,  H04L47/32 ,  G06F9/54 ,  G06F13/14 ,  G06F9/50 ,  H04L47/22 ,  H04L47/52 ,  H04L47/6275 ,  H04L45/24 ,  H04L45/7453 ,  H04L45/16 ,  H04L69/22 ,  H04L47/762 ,  H04L47/78 ,  H04L47/20 ,  H04L49/9047 ,  H04L1/00 ,  H04L43/0876 ,  H04L47/2466 ,  H04L47/625 ,  H04L69/28

CPC classification number: H04L45/28 ,  G06F9/505 ,  G06F9/546 ,  G06F12/0862 ,  G06F12/1036 ,  G06F12/1063 ,  G06F13/14 ,  G06F13/16 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F15/17331 ,  H04L1/0083 ,  H04L43/0876 ,  H04L43/10 ,  H04L45/021 ,  H04L45/028 ,  H04L45/122 ,  H04L45/123 ,  H04L45/125 ,  H04L45/16 ,  H04L45/20 ,  H04L45/22 ,  H04L45/24 ,  H04L45/38 ,  H04L45/42 ,  H04L45/46 ,  H04L45/566 ,  H04L45/70 ,  H04L45/745 ,  H04L45/7453 ,  H04L47/11 ,  H04L47/12 ,  H04L47/122 ,  H04L47/18 ,  H04L47/20 ,  H04L47/22 ,  H04L47/24 ,  H04L47/2441 ,  H04L47/2466 ,  H04L47/2483 ,  H04L47/30 ,  H04L47/32 ,  H04L47/323 ,  H04L47/34 ,  H04L47/39 ,  H04L47/52 ,  H04L47/621 ,  H04L47/626 ,  H04L47/629 ,  H04L47/6235 ,  H04L47/6275 ,  H04L47/76 ,  H04L47/762 ,  H04L47/781 ,  H04L47/80 ,  H04L49/101 ,  H04L49/15 ,  H04L49/30 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/90 ,  H04L49/9005 ,  H04L49/9021 ,  H04L49/9036 ,  H04L49/9047 ,  H04L67/1097 ,  H04L69/22 ,  H04L69/40 ,  G06F2212/50 ,  G06F2213/0026 ,  G06F2213/3808 ,  H04L69/28

Abstract: A network interface controller (NIC) capable of efficient memory access is provided. The NIC can be equipped with an operation logic block, a signaling logic block, and a tracking logic block. The operation logic block can maintain an operation group associated with packets requesting an operation on a memory segment of a host device of the NIC. The signaling logic block can determine whether a packet associated with the operation group has arrived at or departed from the NIC. Furthermore, the tracking logic block can determine that a request for releasing the memory segment has been issued. The tracking logic block can then determine whether at least one packet associated with the operation group is under processing in the NIC. If no packet associated with the operation group is under processing in the NIC, tracking logic block can notify the host device that the memory segment can be released.

公开(公告)号：US20230231818A1

公开(公告)日：2023-07-20

申请号：US17580367

申请日：2022-01-20

Applicant: Pensando Systems Inc.

Inventor： Michael Brian Galles ,  Vipin Jain

IPC: H04L49/00 ,  H04L41/5019 ,  H04L47/32 ,  H04L69/22

CPC classification number: H04L49/3018 ,  H04L41/5019 ,  H04L47/32 ,  H04L69/22

Abstract: A network appliance can have an input port that can receive network packets at line rate, two or more ingress queues, a line rate classification circuit that can place the network packets on the ingress queues at the line rate, a packet buffer that can store the network packets, and a sub line rate packet processing circuit that can process the network packets that are stored in the packet buffer. The line rate classification circuit can place a network packet on one of the ingress queues based on the network packet's packet contents. A buffer scheduler can select network packets for processing by a sub line rate packet processing circuit based on the priority levels of the ingress to queues.

公开(公告)号：US20230224262A1

公开(公告)日：2023-07-13

申请号：US17648260

申请日：2022-01-18

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ioannis (Giannis) Patronas ,  Michael Gandelman ,  Liron Mula ,  Aviad Levy ,  Lion Levi ,  Jose Yallouz ,  Paraskevas Bakopoulos ,  Elad Mentovich

IPC: H04L49/00 ,  H04L49/101

CPC classification number: H04L49/3027 ,  H04L49/101 ,  H04L49/3018

Abstract: Switches for performing packet switching and associated methods are provided. An example switch includes an ingress port for receiving a packet. The switch includes a plurality of egress ports for discharging the packet from the switch. The switch includes a plurality of egress queues with each egress queue associated with one of the plurality of egress ports. The switch includes a control plane configured to determine a descriptor associated with a packet, determine a first egress port from which to discharge the at least one packet and to transmit the descriptor to an egress queue associated with the first egress port. The switch includes a descriptor crossbar configured to transmit the descriptor from the egress queue to a second egress port of the plurality of egress ports. The switch includes a packet crossbar configured to transmit the at least one packet from the ingress port to the second egress port.

公开(公告)号：US20180331964A1

公开(公告)日：2018-11-15

申请号：US15594824

申请日：2017-05-15

Applicant: Nokia Solutions and Networks Oy

Inventor： Guillermo Pocovi ,  Klaus lngemann Pedersen ,  Beatriz Soret

IPC: H04L12/851 ,  H04L12/937 ,  H04L12/863 ,  H04L12/935 ,  H04L12/803

CPC classification number: H04L47/2483 ,  H04L5/0037 ,  H04L5/0044 ,  H04L5/0057 ,  H04L5/0064 ,  H04L5/0071 ,  H04L5/0075 ,  H04L5/0087 ,  H04L47/125 ,  H04L47/56 ,  H04L47/6215 ,  H04L49/254 ,  H04L49/30 ,  H04L49/3018 ,  H04W72/00

Abstract: One or more of multiple UEs with a pending payload are assigned to individual sets of PRBs. The allocating assigns X of N total PRBs to be transmitted, X

公开(公告)号：US09838276B2

公开(公告)日：2017-12-05

申请号：US15397676

申请日：2017-01-03

Applicant: Nicira, Inc.

Inventor： Justin Pettit ,  Martin Casado ,  Teemu Koponen ,  Bruce Davie ,  W. Andrew Lambeth

IPC: H04L12/801 ,  H04L12/26 ,  H04L12/947 ,  H04L12/935

CPC classification number: H04L43/026 ,  H04L43/16 ,  H04L47/11 ,  H04L47/125 ,  H04L49/252 ,  H04L49/3009 ,  H04L49/3018 ,  H04L67/10

Abstract: Some embodiments provide a forwarding element that inspects the size of each of several packets in a data flow to determine whether the data flow is an elephant flow. The forwarding element inspects the size because, in order for the packet to be of a certain size, the data flow had to already have gone through a slow start in which smaller packets are transferred and by definition be an elephant flow. When the forwarding element receives a packet in a data flow, the forwarding element identifies the size of the packet. The forwarding element then determines if the size of the packet is greater than a threshold size. If the size is greater, the forwarding element specifies that the packet's data flow is an elephant flow.

公开(公告)号：US20170222955A1

公开(公告)日：2017-08-03

申请号：US15413930

申请日：2017-01-24

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Ming-I KUO

IPC: H04L12/931 ,  H04L12/861 ,  H04L29/06

CPC classification number: H04L49/505 ,  H04L43/026 ,  H04L47/32 ,  H04L49/201 ,  H04L49/3018 ,  H04L49/50 ,  H04L49/501 ,  H04L49/9047 ,  H04L69/22 ,  H04L69/28

Abstract: A method for interrupting a packet storm in a server is implemented by a baseboard management controller (BMC) included in the server and includes the steps of: assigning a setting value included in firmware of the BMC to a first value so as to enable receipt of specific packets from a network, the specific packets being transmitted using a specific routing scheme; determining whether a packet storm has occurred according to a number of the specific packets that are received; and assigning the setting value to a second value so as to disable receipt of the specific packets when it is determined that the packet storm has occurred.