公开(公告)号：US20240332302A1

公开(公告)日：2024-10-03

申请号：US18129874

申请日：2023-04-02

申请人： Intel Corporation

发明人： Joseph D’SILVA ,  Mauro J. KOBRINSKY ,  Debaleena NANDI ,  Ehren MANNEBACH ,  Shaun MILLS

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L27/0924 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696

摘要： Integrated circuit structures having backside conductive source or drain contacts having enhanced contact area, and methods of fabricating integrated circuit structures having backside conductive source or drain contacts having enhanced contact area, are described. For example, an integrated circuit structure includes a sub-fin structure over a vertical stack of horizontal nanowires or a fin. An epitaxial source or drain structure is laterally adjacent to and coupled to the vertical stack of horizontal nanowires or the fin. The epitaxial source or drain structure has a recess within a laterally surrounding outer portion. A conductive source or drain contact is laterally adjacent to the sub-fin structure and is over and in contact with the epitaxial source or drain structure. The conductive source or drain contact is within the recess in the epitaxial source or drain structure.

公开(公告)号：US20240322024A1

公开(公告)日：2024-09-26

申请号：US18186211

申请日：2023-03-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Han Tsai ,  Pin Chun Shen ,  Ta-Chun LIN ,  Chun-Sheng Liang

IPC分类号： H01L29/775 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/775 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553

摘要： A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes first semiconductor channel layers, second semiconductor channel layers, a dielectric wall, a gate structure, a source/drain electrode and an inner spacer. The first semiconductor channel layers are stacked vertically apart along a first direction over a substrate. The second semiconductor channel layers are stacked vertically apart along the first direction over the substrate. The dielectric wall is disposed between and separates the first semiconductor channel layers and the second first semiconductor channel layers, wherein the dielectric wall comprises a liner and a dielectric wall material disposed over the liner. The gate structure extends along a second direction perpendicular to the first direction disposed crossing over a channel region of the first fin structure and a channel region of the second fin structure. The source/drain electrode is in contact with the first semiconductor channel layers. The inner spacer is enclosed by the first semiconductor channel layers, the gate structure, the dielectric wall and the source/drain electrode, wherein the inner spacer is in contact with the dielectric wall material of the dielectric wall.

公开(公告)号：US20240321989A1

公开(公告)日：2024-09-26

申请号：US18397561

申请日：2023-12-27

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Gunho JO ,  Heesub KIM ,  Seunghyun LIM ,  Bomi KIM ,  Eunho CHO

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L29/42392 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

摘要： A semiconductor device includes a substrate, an active pattern including a lower pattern extending in a first direction and a plurality of sheet patterns above an upper surface of the lower pattern and spaced apart from the lower pattern in a second direction substantially perpendicular to the first direction, a gate structure on the lower pattern and including a gate electrode and a gate insulating film, the gate electrode and the gate insulating film at least partially surrounding the plurality of sheet patterns, a first gate capping pattern on the gate structure and above the plurality of sheet patterns in the second direction, a gate spacer extending along a side wall of the gate structure, and a second gate capping pattern extending along an upper surface of the gate structure and an upper surface of the first gate capping pattern.

公开(公告)号：US20240321979A1

公开(公告)日：2024-09-26

申请号：US18544560

申请日：2023-12-19

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Davin LEE ,  Hyunseung SONG

IPC分类号： H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/41733 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

摘要： An integrated circuit device includes: a substrate including a first and second device regions; a first and third fin-type active regions extending in a first direction in the first device region; a second and fourth fin-type active regions extending in the first direction in the second device region; a gate line extending in a second direction crossing the first direction in the first through fourth fin-type active regions; a first source/drain region adjacent to the gate line in the first fin-type active region; a second source/drain region adjacent to the gate line in the second fin-type active region; a first source/drain contact connected to the first source/drain region; and a second source/drain contact connected to the second source/drain region; wherein the first source/drain contact includes a first short metal plug and a first conductive barrier layer at least partially surrounding a portion of sidewalls of the first short metal plug.

公开(公告)号：US20240321978A1

公开(公告)日：2024-09-26

申请号：US18125456

申请日：2023-03-23

申请人： Intel Corporation

发明人： Leonard P. Guler ,  Shengsi Liu ,  Baofu Zhu ,  Charles H. Wallace ,  Clifford J. Engel ,  Gary Allen ,  Saurabh Acharya ,  Thomas Obrien

IPC分类号： H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L29/41733 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

摘要： Techniques are provided herein to form semiconductor devices that include a contact over a given source or drain region that extends over the top of an adjacent source or drain region without contacting it. In an example, a semiconductor device includes a gate structure around a fin of semiconductor material that extends from a source or drain region, or one or more nanowires or nanoribbons or nanosheets of semiconductor material that extend from the source or drain region. A conductive contact is formed over the source or drain region that extends laterally across the source/drain trench above an adjacent source or drain region without contacting the adjacent source or drain region. The contact may extend along the source/drain trench through a dielectric wall (e.g., a gate cut) that extends orthogonally through the source/drain trench.

公开(公告)号：US20240321886A1

公开(公告)日：2024-09-26

申请号：US18605400

申请日：2024-03-14

申请人： Samsung Electronics Co., Ltd.

发明人： Kyunghee Cho ,  Myungil Kang ,  Kyungho Kim ,  Kyowook Lee ,  Seunghun Lee

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

摘要： A stacked integrated circuit device includes a plurality of transistors including a pair of pull-up transistors in a first layer, a pair of pull-down transistors in a second layer that is at a different vertical level than the first layer, and a pair of pass-gate transistors in the first or second layer, a contact configured to electrically connect a source/drain region of one of the pull-up transistors, a source/drain region of one of the pull-down transistors, and a source/drain region of one of the pass-gate transistors to one another, a gate contact configured to connect a gate electrode of the other pull-up transistor to a gate electrode of the other pull-down transistor, and an upper wire on the contact and the gate contact, the upper wire extending in a first horizontal direction and being connected to the contact and the gate contact.

公开(公告)号：US20240321747A1

公开(公告)日：2024-09-26

申请号：US18123613

申请日：2023-03-20

申请人： International Business Machines Corporation

发明人： Ruilong Xie ,  Christopher J. Penny ,  Kisik Choi ,  Koichi Motoyama ,  Nicholas Anthony Lanzillo ,  Chih-Chao Yang

IPC分类号： H01L23/528 ,  H01L21/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L23/5286 ,  H01L21/7806 ,  H01L21/823807 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

摘要： A semiconductor structure is provided that includes a plurality of backside power islands, rather than backside power rails. The backside power islands are present in a first device track and a second device track. Each backside power island located in the first device track and the second device track are isolated by a first cut region, and the backside power islands that are located in the first device track are separated from the backside power islands located in the second device track by a second cut region. The second cut region is oriented perpendicular to the first cut region.

公开(公告)号：US20240321688A1

公开(公告)日：2024-09-26

申请号：US18393837

申请日：2023-12-22

申请人： SAMSUNG ELECTRONICS CO., LTD

发明人： SUNGMIN KIM

IPC分类号： H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

摘要： A semiconductor device includes a front-side wiring structure connected to a signal line, a back-side wiring structure arranged below the front-side wiring structure and connected to a power line, and an electronic element between the front-side wiring structure and the back-side wiring structure, wherein the electronic element includes a plurality of gate structures, each of the plurality of gate structures includes a gate electrode, a capping film, and a gate spacer, and the capping film includes a first capping film and a second capping film, the first capping film being on a bottom surface of the gate electrode, and the second capping film being on a top surface of the gate electrode.

公开(公告)号：US12100712B2

公开(公告)日：2024-09-24

申请号：US18176626

申请日：2023-03-01

申请人： InnoLux Corporation

发明人： An-Chang Wang ,  Bo-Chin Tsuei ,  Hsia-Ching Chu ,  Ming-Chien Sun

IPC分类号： H01L27/12 ,  H01L29/417 ,  G02F1/1368

CPC分类号： H01L27/124 ,  H01L27/1218 ,  H01L29/41733 ,  G02F1/1368

摘要： A substrate assembly includes: a substrate; a gate structure disposed on the substrate; a conductive line disposed on the substrate, wherein from a top view, the conductive line extends along a first direction; and a conductive structure disposed on the substrate, wherein from the top view, the conductive structure is adjacent to the conductive line and separated from the conductive line, and the conductive structure has an overlapping region overlapping the gate structure, wherein from the top view, the overlapping region extends along a second direction, the first direction and the second direction are different, the overlapping region comprises a first end portion, and the first end portion has a curved shape.

公开(公告)号：US12100709B2

公开(公告)日：2024-09-24

申请号：US18480552

申请日：2023-10-04

申请人： Japan Display Inc.

发明人： Isao Suzumura ,  Kazufumi Watabe ,  Yoshinori Ishii ,  Hidekazu Miyake ,  Yohei Yamaguchi

IPC分类号： H01L27/12 ,  G02F1/133 ,  G02F1/1362 ,  G02F1/1368 ,  H01L29/24 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H10K59/121

CPC分类号： H01L27/1225 ,  G02F1/13306 ,  G02F1/136209 ,  G02F1/1368 ,  H01L27/1251 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/78633 ,  H01L29/78675 ,  H01L29/7869 ,  G02F1/13685 ,  G02F2202/10 ,  G02F2202/104 ,  H10K59/1213

摘要： The object of the present invention is to make it possible to form an LTPS TFT and an oxide semiconductor TFT on the same substrate. A display device includes a substrate having a display region in which pixels are formed. The pixel includes a first TFT using an oxide semiconductor 109. An oxide film 110 as an insulating material is formed on the oxide semiconductor 109. A gate electrode 111 is formed on the oxide film 110. A first electrode 115 is connected to a drain of the first TFT via a first through hole formed in the oxide film 110. A second electrode 116 is connected to a source of the first TFT via a second through hole formed in the oxide film 110.