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    SEMICONDUCTOR PACKAGE
    1.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230063578A1

    公开(公告)日：2023-03-02

    申请号：US17712489

    申请日：2022-04-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Eunho CHO ,  Jihwang KIM ,  Sunchul KIM

    IPC: H01L23/498 ,  H01L23/31

    Abstract: A semiconductor package is provided. The semiconductor package includes: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate, and electrically connected to the lower wiring layer; an upper substrate disposed on the semiconductor chip, and including an upper wiring layer; a first connection structure disposed on the lower wiring layer, and having a first hollow open toward the upper substrate; a second connection structure disposed below the upper wiring layer, and having a second hollow open toward the lower substrate; a conductive connection member disposed between the first connection structure and the second connection structure, and filling at least a portion of the first hollow; and an encapsulant disposed between the lower substrate and the upper substrate, and encapsulating at least a portion of each of the semiconductor chip, the first connection structure and the second connection structure.

    SEMICONDUCTOR PACKAGE
    2.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230112061A1

    公开(公告)日：2023-04-13

    申请号：US17826505

    申请日：2022-05-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Eunho CHO ,  Jihwang KIM ,  Jongbo SHIM

    IPC: H01L23/473 ,  H01L25/065 ,  H01L23/00

    Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, a chip connection terminal configured to electrically connect the first semiconductor chip to the second semiconductor chip, an underfill layer disposed between the first semiconductor chip and the second semiconductor chip and surrounding the chip connection terminal, a vertical porous structure filling spaces of a plurality of vertical cooling channels passing through the first semiconductor chip, the second semiconductor chip, and the underfill layer in a vertical direction, and having a plurality of cooling holes, and a cooling fluid provided to the plurality of cooling holes of the vertical porous structure to flow inside the plurality of vertical cooling channels.

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    4.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240194536A1

    公开(公告)日：2024-06-13

    申请号：US18215459

    申请日：2023-06-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Heesub KIM ,  GUNHO JO ,  BOMI KIM ,  Eunho CHO

    IPC: H01L21/8234 ,  H01L27/088

    CPC classification number: H01L21/823481 ,  H01L27/088

    Abstract: A method for manufacturing a semiconductor device includes: forming a semiconductor structure and a dummy structure on a substrate; forming a first insulating layer between the semiconductor structure and the dummy structure; forming a first space by removing the dummy structure; forming an isolation pattern in the first space; forming a main gate sacrificial pattern crossing the first direction to overlap the semiconductor structure; forming second spaces by removing portions of the semiconductor structure at both sides of the main gate sacrificial pattern, and forming source/drain patterns in the second spaces; forming a second insulating layer on the source/drain patterns; forming a third space by removing the main gate sacrificial pattern, and forming a gate electrode in the third space; and forming fourth spaces by removing the second insulating layer, and forming, in the fourth spaces, contact structures connected to the source/drain patterns and disposed on both sides of the isolation pattern.

    SEMICONDUCTOR DEVICE
    5.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240321989A1

    公开(公告)日：2024-09-26

    申请号：US18397561

    申请日：2023-12-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Gunho JO ,  Heesub KIM ,  Seunghyun LIM ,  Bomi KIM ,  Eunho CHO

    IPC: H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775

    CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

    Abstract: A semiconductor device includes a substrate, an active pattern including a lower pattern extending in a first direction and a plurality of sheet patterns above an upper surface of the lower pattern and spaced apart from the lower pattern in a second direction substantially perpendicular to the first direction, a gate structure on the lower pattern and including a gate electrode and a gate insulating film, the gate electrode and the gate insulating film at least partially surrounding the plurality of sheet patterns, a first gate capping pattern on the gate structure and above the plurality of sheet patterns in the second direction, a gate spacer extending along a side wall of the gate structure, and a second gate capping pattern extending along an upper surface of the gate structure and an upper surface of the first gate capping pattern.

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