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    SEMICONDUCTOR PACKAGE
    1.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230063578A1

    公开(公告)日：2023-03-02

    申请号：US17712489

    申请日：2022-04-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Eunho CHO ,  Jihwang KIM ,  Sunchul KIM

    IPC: H01L23/498 ,  H01L23/31

    Abstract: A semiconductor package is provided. The semiconductor package includes: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate, and electrically connected to the lower wiring layer; an upper substrate disposed on the semiconductor chip, and including an upper wiring layer; a first connection structure disposed on the lower wiring layer, and having a first hollow open toward the upper substrate; a second connection structure disposed below the upper wiring layer, and having a second hollow open toward the lower substrate; a conductive connection member disposed between the first connection structure and the second connection structure, and filling at least a portion of the first hollow; and an encapsulant disposed between the lower substrate and the upper substrate, and encapsulating at least a portion of each of the semiconductor chip, the first connection structure and the second connection structure.

    SEMICONDUCTOR PACKAGE
    2.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210066244A1

    公开(公告)日：2021-03-04

    申请号：US16821342

    申请日：2020-03-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sunchul KIM ,  Kyungsuk OH ,  Taehun KIM ,  Pyoungwan KIM

    IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00

    Abstract: A semiconductor package including a package substrate; a first semiconductor chip on the package substrate; a second semiconductor chip on an upper surface of the first semiconductor chip; an insulating layer on surfaces of the first semiconductor chip and the second semiconductor chip; a heat dissipation member on the insulating layer such that the heat dissipation member includes a region on an upper surface of the first semiconductor chip on which the second semiconductor chip is not disposed, and a region on an upper surface of the second semiconductor chip; a molding member on the package substrate and encapsulating the first semiconductor chip, the second semiconductor chip, and the heat dissipation member such that the molding member exposes at least a portion of an upper surface of the heat dissipation member; and a reinforcing member on the heat dissipation member and the molding member.

    SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING SAME
    4.
    发明申请
    SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING SAME 审中-公开

    公开(公告)号：US20190019758A1

    公开(公告)日：2019-01-17

    申请号：US15956414

    申请日：2018-04-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Uk KIM ,  Sunchul KIM ,  Jinkyeong SEOL ,  BYOUNG WOOK JANG

    IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

    Abstract: A semiconductor package and a method manufacturing the same are disclosed. At least one semiconductor chip is mounted on a package substrate. An insulative mold layer is formed at sides of the semiconductor chip having at least one recess in a region in which conductive connection members are formed, the recess defining one or more protrusions within the mold layer. An interposer is positioned on the protrusions with the conductive connection members connecting and providing electrical connections between conductive pads on the upper surface of the package and conductive pads on the lower surface of the package substrate. The protrusions may position the interposer in the vertical direction by defining the vertical spacing between the lower surface of the interposer and the upper surface of the package substrate. The protrusions may also position the interposer in one or more horizontal directions and/or prevent substantial movement during connecting of the interposer to the package substrate. An under-fill resin layer may be injected into remaining space between the interposer and the package substrate.

    SEMICONDUCTOR PACKAGE
    5.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210082881A1

    公开(公告)日：2021-03-18

    申请号：US16809837

    申请日：2020-03-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinkyeong SEOL ,  Sunchul KIM ,  Pyoungwan KIM

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/16 ,  H01L23/532

    Abstract: A semiconductor package including a substrate; a semiconductor stack on the substrate; an underfill between the substrate and the semiconductor stack; an insulating layer conformally covering surfaces of the semiconductor stack and the underfill; a chimney on the semiconductor stack; and a molding member surrounding side surfaces of the chimney, wherein the semiconductor stack has a first upper surface that is a first distance from the substrate and a second upper surface that is a second distance from the substrate, the first distance being greater than the second distance, wherein the chimney includes a thermally conductive filler on the first and second upper surfaces of the semiconductor stack, the thermally conductive filler having a flat upper surface; a thermally conductive spacer on the thermally conductive filler; and a protective layer on the thermally conductive spacer, and wherein an upper surface of the thermally conductive spacer is exposed.

    SEMICONDUCTOR PACKAGE
    6.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210057380A1

    公开(公告)日：2021-02-25

    申请号：US16816593

    申请日：2020-03-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sunchul KIM ,  Kyungsuk OH ,  Taehun KIM ,  Pyoungwan KIM ,  Soohwan LEE

    IPC: H01L25/065 ,  H01L23/367 ,  H01L23/31 ,  H01L25/00

    Abstract: A semiconductor package includes a package substrate, a first semiconductor chip disposed on the package substrate, at least one second semiconductor chip disposed on a region of an upper surface of the first semiconductor chip, a heat dissipation member disposed in another region of the upper surface of the first semiconductor chip and at least a region of an upper surface of the second semiconductor chip, and having an upper surface in which at least one trench is formed, and a molding member covering the first semiconductor chip, the second semiconductor chip, an upper surface of the package substrate, and side surfaces of the heat dissipation member, and filling the at least one trench while exposing the upper surface of the heat dissipation member.

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