公开(公告)号：US20150155216A1

公开(公告)日：2015-06-04

申请号：US14491957

申请日：2014-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： JONGKOOK KIM ,  BYOUNG WOOK JANG

IPC: H01L23/31 ,  H01L21/02 ,  H01L21/3105 ,  H01L23/00

CPC classification number: H01L23/3171 ,  H01L23/3114 ,  H01L23/3157 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06132 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/07025 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00014

Abstract: A semiconductor chip comprising: a substrate; a plurality of pads disposed on the substrate; and a plurality of passivation patterns laterally separated from each other on the substrate, each of the passivation patterns including a plurality of openings, the openings exposing at least one pad of the pads, and the passivation patterns having a thermal expansion coefficient different from a thermal expansion coefficient of the substrate.

Abstract translation: 一种半导体芯片，包括：基板; 设置在所述基板上的多个焊盘; 以及在衬底上彼此横向分离的多个钝化图案，每个钝化图案包括多个开口，所述开口暴露至少一个衬垫垫，并且所述钝化图案具有不同于热的热膨胀系数 底物的膨胀系数。

公开(公告)号：US20200098734A1

公开(公告)日：2020-03-26

申请号：US16698749

申请日：2019-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANHEE JEONG ,  HYUNKI KIM ,  JUNWOO PARK ,  BYOUNG WOOK JANG ,  SUNCHUL KIM ,  SU-MIN PARK ,  PYOUNGWAN KIM ,  INKU KANG ,  HEEYEOL KIM

IPC: H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package includes a semiconductor chip disposed on a first substrate, a mold layer covering a sidewall of the semiconductor chip and including a through-hole, a second substrate disposed on the semiconductor chip, a connection terminal disposed between the first substrate and the second substrate and provided in the through-hole, and an underfill resin layer extending from between the semiconductor chip and the second substrate into the through-hole.

公开(公告)号：US20190019758A1

公开(公告)日：2019-01-17

申请号：US15956414

申请日：2018-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uk KIM ,  Sunchul KIM ,  Jinkyeong SEOL ,  BYOUNG WOOK JANG

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package and a method manufacturing the same are disclosed. At least one semiconductor chip is mounted on a package substrate. An insulative mold layer is formed at sides of the semiconductor chip having at least one recess in a region in which conductive connection members are formed, the recess defining one or more protrusions within the mold layer. An interposer is positioned on the protrusions with the conductive connection members connecting and providing electrical connections between conductive pads on the upper surface of the package and conductive pads on the lower surface of the package substrate. The protrusions may position the interposer in the vertical direction by defining the vertical spacing between the lower surface of the interposer and the upper surface of the package substrate. The protrusions may also position the interposer in one or more horizontal directions and/or prevent substantial movement during connecting of the interposer to the package substrate. An under-fill resin layer may be injected into remaining space between the interposer and the package substrate.

公开(公告)号：US20180145061A1

公开(公告)日：2018-05-24

申请号：US15818346

申请日：2017-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANHEE JEONG ,  HYUNKI KIM ,  JUNWOO PARK ,  BYOUNG WOOK JANG ,  SUNCHUL KIM ,  SU-MIN PARK ,  PYOUNGWAN KIM ,  INKU KANG ,  HEEYEOL KIM

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/214 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00

Abstract: A semiconductor package includes a semiconductor chip disposed on a first substrate, a mold layer covering a sidewall of the semiconductor chip and including a through-hole, a second substrate disposed on the semiconductor chip, a connection terminal disposed between the first substrate and the second substrate and provided in the through-hole, and an underfill resin layer extending from between the semiconductor chip and the second substrate into the through-hole.