公开(公告)号：US20200043854A1

公开(公告)日：2020-02-06

申请号：US16424000

申请日：2019-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUHYEON OH ,  SUNCHUL KIM ,  HYUNKI KIM

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31

Abstract: A semiconductor package includes a first substrate, a second substrate provided on the first substrate, a semiconductor chip provided between the first substrate and the second substrate, solder structures extending between the first substrate and the second substrate and spaced apart from the semiconductor chip, and bumps provided between the semiconductor chip and the second substrate. The solder structures electrically connect the first substrate and the second substrate.

公开(公告)号：US20250079232A1

公开(公告)日：2025-03-06

申请号：US18596869

申请日：2024-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TAEJAE PARK ,  YONGKWAN LEE ,  SUNCHUL KIM ,  JUNGSOO JEON

IPC: H01L21/687 ,  H01L21/48 ,  H01L21/67 ,  H01L21/683

Abstract: A semiconductor package bonding tool includes a bonding plate and bonding blocks disposed on a bottom surface of the bonding plate. The bonding plate include first vacuum holes that vertically penetrate the bonding plate. The first vacuum holes connect a top surface of the bonding plate to the bottom surface of the bonding plate. Each of the bonding blocks includes a bonding stage disposed below a respective first vacuum hole of the first vacuum holes. The bonding stage includes a trench hole upwardly recessed from a bottom surface of the bonding stage, and a connection hole connecting a top surface of the bonding stage to the trench hole. A length in a horizontal direction of the trench hole is greater than that of the connection hole.

公开(公告)号：US20230126102A1

公开(公告)日：2023-04-27

申请号：US17876240

申请日：2022-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNCHUL KIM ,  YONGHYUN KIM ,  SEUNGHWAN BAEK ,  MINJAE LEE ,  JUHYUNG LEE

IPC: H01L23/498 ,  H01L25/10

Abstract: A semiconductor package structure includes a semiconductor chip on a package substrate; a lower connection bump on the package substrate; and an interposer substrate on the lower connection bump on the package substrate and an upper surface of the semiconductor chip. The semiconductor package structure includes an upper connection bump on a lower surface of the interposer substrate; and a support structure on a lower surface of the interposer substrate, spaced apart from the upper connection bump to provide support between the package substrate and the interposer substrate. The upper connection bump and the lower connection bump constitute a connection bump structure, and the support structure includes a metal core ball and a ball cover layer surrounding the metal core ball, wherein the ball cover layer is formed to gradually decrease in thickness in a direction from the interposer substrate to the package substrate cross-section.

公开(公告)号：US20200098734A1

公开(公告)日：2020-03-26

申请号：US16698749

申请日：2019-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANHEE JEONG ,  HYUNKI KIM ,  JUNWOO PARK ,  BYOUNG WOOK JANG ,  SUNCHUL KIM ,  SU-MIN PARK ,  PYOUNGWAN KIM ,  INKU KANG ,  HEEYEOL KIM

IPC: H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package includes a semiconductor chip disposed on a first substrate, a mold layer covering a sidewall of the semiconductor chip and including a through-hole, a second substrate disposed on the semiconductor chip, a connection terminal disposed between the first substrate and the second substrate and provided in the through-hole, and an underfill resin layer extending from between the semiconductor chip and the second substrate into the through-hole.

公开(公告)号：US20180145061A1

公开(公告)日：2018-05-24

申请号：US15818346

申请日：2017-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANHEE JEONG ,  HYUNKI KIM ,  JUNWOO PARK ,  BYOUNG WOOK JANG ,  SUNCHUL KIM ,  SU-MIN PARK ,  PYOUNGWAN KIM ,  INKU KANG ,  HEEYEOL KIM

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/214 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00

Abstract: A semiconductor package includes a semiconductor chip disposed on a first substrate, a mold layer covering a sidewall of the semiconductor chip and including a through-hole, a second substrate disposed on the semiconductor chip, a connection terminal disposed between the first substrate and the second substrate and provided in the through-hole, and an underfill resin layer extending from between the semiconductor chip and the second substrate into the through-hole.