公开(公告)号：US20210066244A1

公开(公告)日：2021-03-04

申请号：US16821342

申请日：2020-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunchul KIM ,  Kyungsuk OH ,  Taehun KIM ,  Pyoungwan KIM

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor package including a package substrate; a first semiconductor chip on the package substrate; a second semiconductor chip on an upper surface of the first semiconductor chip; an insulating layer on surfaces of the first semiconductor chip and the second semiconductor chip; a heat dissipation member on the insulating layer such that the heat dissipation member includes a region on an upper surface of the first semiconductor chip on which the second semiconductor chip is not disposed, and a region on an upper surface of the second semiconductor chip; a molding member on the package substrate and encapsulating the first semiconductor chip, the second semiconductor chip, and the heat dissipation member such that the molding member exposes at least a portion of an upper surface of the heat dissipation member; and a reinforcing member on the heat dissipation member and the molding member.

公开(公告)号：US20160099213A1

公开(公告)日：2016-04-07

申请号：US14721435

申请日：2015-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yujung TAE ,  Pyoungwan KIM

IPC: H01L23/538

CPC classification number: H01L23/5389 ,  H01L21/568 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/19 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2224/83005

Abstract: A semiconductor package includes a package substrate with a cavity, a plurality of semiconductor chips vertically stacked in the cavity, a first insulating layer on a first surface of the package substrate, a first interconnection layer on the first insulating layer, a second insulating layer on a second surface of the package substrate opposite the first surface, and a second interconnection layer on the second insulating layer.

Abstract translation: 半导体封装包括具有空腔的封装衬底，垂直堆叠在腔中的多个半导体芯片，在封装衬底的第一表面上的第一绝缘层，第一绝缘层上的第一互连层，第二绝缘层 所述封装基板的与所述第一表面相对的第二表面，以及在所述第二绝缘层上的第二互连层。

公开(公告)号：US20210082881A1

公开(公告)日：2021-03-18

申请号：US16809837

申请日：2020-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinkyeong SEOL ,  Sunchul KIM ,  Pyoungwan KIM

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/16 ,  H01L23/532

Abstract: A semiconductor package including a substrate; a semiconductor stack on the substrate; an underfill between the substrate and the semiconductor stack; an insulating layer conformally covering surfaces of the semiconductor stack and the underfill; a chimney on the semiconductor stack; and a molding member surrounding side surfaces of the chimney, wherein the semiconductor stack has a first upper surface that is a first distance from the substrate and a second upper surface that is a second distance from the substrate, the first distance being greater than the second distance, wherein the chimney includes a thermally conductive filler on the first and second upper surfaces of the semiconductor stack, the thermally conductive filler having a flat upper surface; a thermally conductive spacer on the thermally conductive filler; and a protective layer on the thermally conductive spacer, and wherein an upper surface of the thermally conductive spacer is exposed.

公开(公告)号：US20210057380A1

公开(公告)日：2021-02-25

申请号：US16816593

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunchul KIM ,  Kyungsuk OH ,  Taehun KIM ,  Pyoungwan KIM ,  Soohwan LEE

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/31 ,  H01L25/00

Abstract: A semiconductor package includes a package substrate, a first semiconductor chip disposed on the package substrate, at least one second semiconductor chip disposed on a region of an upper surface of the first semiconductor chip, a heat dissipation member disposed in another region of the upper surface of the first semiconductor chip and at least a region of an upper surface of the second semiconductor chip, and having an upper surface in which at least one trench is formed, and a molding member covering the first semiconductor chip, the second semiconductor chip, an upper surface of the package substrate, and side surfaces of the heat dissipation member, and filling the at least one trench while exposing the upper surface of the heat dissipation member.

公开(公告)号：US20250167089A1

公开(公告)日：2025-05-22

申请号：US18734563

申请日：2024-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin MOON ,  Pyoungwan KIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package includes a lower redistribution wiring layer having first redistribution wirings, the lower redistribution wiring layer having a first region and a second region surrounding the first region, a semiconductor chip on the first region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings, at least one bridge die stack on the second region of the lower redistribution wiring layer and including a plurality of bridge dies sequentially stacked on one another, each of the bridge dies including a plurality of through-vias that are electrically connected to the first redistribution wirings, a sealing member on the lower redistribution wiring layer covering the semiconductor chip and the at least one bridge die stack and an upper redistribution wiring layer on the sealing member and including second redistribution wirings electrically connected to the through-vias of the at least one bridge die stack.

公开(公告)号：US20250079395A1

公开(公告)日：2025-03-06

申请号：US18815924

申请日：2024-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin MOON ,  Pyoungwan KIM

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/66

Abstract: A method of manufacturing a semiconductor package, the method includes preparing a first semiconductor chip including a plurality of first upper connection pads, disposing a plurality of connection bumps electrically connected to the plurality of first upper connection pads on the first semiconductor chip, forming an insulating adhesive layer at least partially covering the plurality of connection bumps on an upper surface of the first semiconductor chip, removing a plurality of regions to be removed of the insulating adhesive layer, and bonding a second semiconductor chip including a plurality of second lower connection pads on the insulating adhesive layer, wherein each of the plurality of regions to be removed is a portion of the insulating adhesive layer that at least partially overlaps a connection bump among the plurality of corresponding connection bumps in a vertical direction.

公开(公告)号：US20240243054A1

公开(公告)日：2024-07-18

申请号：US18539949

申请日：2023-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin MOON ,  Pyoungwan KIM ,  Giho JEONG

IPC: H01L23/498 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/49838 ,  H01L25/18 ,  H10B80/00 ,  H01L23/3128 ,  H01L23/49894

Abstract: A semiconductor package may include a first wiring structure, a second wiring structure on the first wiring structure, a semiconductor chip between the first wiring structure and the second wiring structure, and an expanded structure that electrically connects the first wiring structure with the second wiring structure and surrounds the semiconductor chip. At least one of the first wiring structure and the second wiring structure may include a first insulating layer on the semiconductor chip and the expanded structure, a first wiring layer on the first insulating layer, a second insulating layer covering the first insulating layer and the first wiring layer, a crack prevention layer on the second insulating layer, and a second wiring layer on the second insulating layer and the crack prevention layer. The second wiring layer may include a pad portion.