公开(公告)号：US20230352529A1

公开(公告)日：2023-11-02

申请号：US17965551

申请日：2022-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gunho JO ,  Byounghak HONG ,  Seungchan YUN ,  Jaejik BAEK

IPC: H01L29/06 ,  H01L27/06 ,  H01L29/786 ,  H01L25/11 ,  H01L21/8234

CPC classification number: H01L29/0673 ,  H01L27/0688 ,  H01L29/78696 ,  H01L25/117 ,  H01L21/823431

Abstract: Provided is a multi-stack semiconductor device that includes: a lower nanosheet transistor including a plurality of lower channel layers surrounded by a gate structure; and an upper nanosheet transistor stacked on the lower nanosheet transistor and including a plurality of upper channel layers surrounded by the gate structure, wherein the lower channel layers have a smaller channel interval than the upper channel layers.

公开(公告)号：US20220336582A1

公开(公告)日：2022-10-20

申请号：US17402214

申请日：2021-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gunho JO ,  Ki-il KIM ,  Byounghak HONG ,  Kang-ill SEO

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66

Abstract: A multi-stack semiconductor device includes: a substrate; and a plurality of multi-stack transistor structures arranged on the substrate in a channel width direction, wherein the multi-stack transistor structure include at least one lower transistor structure and at least one upper transistor structure stacked above the lower transistor structure, wherein the lower and upper transistor structures include at least one channel layer as a current channel, wherein the lower transistor structures of at least two multi-stack transistor structures have different channel-layer widths.

公开(公告)号：US20240321989A1

公开(公告)日：2024-09-26

申请号：US18397561

申请日：2023-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gunho JO ,  Heesub KIM ,  Seunghyun LIM ,  Bomi KIM ,  Eunho CHO

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A semiconductor device includes a substrate, an active pattern including a lower pattern extending in a first direction and a plurality of sheet patterns above an upper surface of the lower pattern and spaced apart from the lower pattern in a second direction substantially perpendicular to the first direction, a gate structure on the lower pattern and including a gate electrode and a gate insulating film, the gate electrode and the gate insulating film at least partially surrounding the plurality of sheet patterns, a first gate capping pattern on the gate structure and above the plurality of sheet patterns in the second direction, a gate spacer extending along a side wall of the gate structure, and a second gate capping pattern extending along an upper surface of the gate structure and an upper surface of the first gate capping pattern.

公开(公告)号：US20230343845A1

公开(公告)日：2023-10-26

申请号：US17891777

申请日：2022-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak HONG ,  Gunho JO ,  Seungchan YUN ,  Jaejik BAEK

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/786 ,  H01L29/417 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L27/088 ,  H01L29/78696 ,  H01L29/41775 ,  H01L29/0673 ,  H01L21/823412 ,  H01L21/823437

Abstract: Provided is a multi-stack semiconductor device that includes: a lower field-effect transistor in which a lower channel structure is surrounded by a lower gate structure including a lower gate dielectric layer, a lower work-function metal layer and a lower gate metal pattern; and an upper field-effect transistor in which an upper channel structure is surrounded by an upper gate structure including an upper gate dielectric layer, an upper work-function metal layer and an upper gate metal pattern, wherein a channel width of the upper channel structure is smaller than a channel width of the lower channel structure, and wherein a replacement metal gate (RMG) inner spacer is formed between the lower work-function metal layer and the upper work-function metal layer at regions where the lower channel structure is not vertically overlapped by the upper channel structure.

公开(公告)号：US20230343825A1

公开(公告)日：2023-10-26

申请号：US17988485

申请日：2022-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Saehan PARK ,  Panjae PARK ,  Seungyoung LEE ,  Byounghak HONG ,  Gunho JO

IPC: H01L29/06 ,  H01L27/06 ,  H01L23/48 ,  H01L29/08 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L29/0673 ,  H01L27/0688 ,  H01L23/481 ,  H01L29/0847 ,  H01L29/78696 ,  H01L27/0886

Abstract: Provided is a three-dimensional stacked (3D-stacked) semiconductor device which includes: a lower active region divided into a lower-1st active sub-region and a lower-2nd active sub-region by at least one lower boundary gate structure; and an upper active region, above the lower active region, divided into an upper-1st active sub-region and an upper-2nd active sub-region by at least one upper boundary gate structure, wherein at least one of the lower boundary gate structure and the upper boundary gate structure is reverse-biased to electrically isolate the lower-1st active sub-region from the lower-2nd active sub-region, and/or electrically isolate the upper-1st active sub-region from the upper-2nd active sub-region