公开(公告)号：US12107013B2

公开(公告)日：2024-10-01

申请号：US17166558

申请日：2021-02-03

Applicant: Taiwan Semicondutor Manufacturing Company Limited

Inventor： Shih-Yao Lin ,  Chih-Han Lin ,  Shu-Yuan Ku ,  Shu-Uei Jang ,  Ya-Yi Tsai ,  I-Wei Yang

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L27/0886

Abstract: A semiconductor device includes a first semiconductor fin extending along a first direction. The semiconductor device includes a second semiconductor fin also extending along the first direction. The semiconductor device includes a dielectric structure disposed between the first and second semiconductor fins. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric structure. The semiconductor device includes a metal gate layer extending along a second direction perpendicular to the first direction, wherein the metal gate layer includes a first portion straddling the first semiconductor fin and a second portion straddling the second semiconductor fin. The gate isolation structure separates the first and second portions of the metal gate layer from each other and includes a bottom portion extending into the dielectric structure.

公开(公告)号：US20240322017A1

公开(公告)日：2024-09-26

申请号：US18737615

申请日：2024-06-07

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Ya-Yi Tsai ,  Yi-Chun Chen ,  Wei-Han Chen ,  Wei-Ting Guo ,  Shu-Yuan Ku

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor substrate; an isolation region disposed on the semiconductor substrate; a plurality of dummy fins disposed over the isolation region and partially extending into the isolation region; and a dielectric material disposed between the plurality of dummy fins, and partially extending through the isolation region and partially into the semiconductor substrate.

公开(公告)号：US20240321880A1

公开(公告)日：2024-09-26

申请号：US18732028

申请日：2024-06-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Yao Lin ,  Chieh-Ning Feng ,  Hsiao Wen Lee ,  Chao-Cheng Chen

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device includes a dielectric fin between a first semiconductor channel and a second semiconductor channel. The semiconductor device includes a first gate structure. The first gate structure includes a first portion and a second portion separated from each other by the dielectric fin. The semiconductor device includes a first gate spacer that extends along sidewalls of the first portion of the first gate structure. The semiconductor device includes a second gate spacer that extends along sidewalls of the second portion of the first gate structure, respectively. At least one of the first gate spacer or second gate spacer has a first portion with a first thickness and a second portion with a second thickness less than the first thickness, and wherein the first portion is closer to the dielectric fin than the second portion.

公开(公告)号：US20240321645A1

公开(公告)日：2024-09-26

申请号：US18188496

申请日：2023-03-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Juntao Li ,  Julien Frougier ,  Nicolas Jean Loubet ,  Chanro Park ,  Min Gyu Sung ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823475 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/088

Abstract: A microelectronic device including a first nanosheet transistor includes a first source/drain and a second nanosheet transistor includes a second source/drain. The first source/drain and the second source/drain are adjacent to each other. Each of the first source/drain and the second source/drain have an asymmetrical profile when cut through the first and second source/drain.

公开(公告)号：US12100770B2

公开(公告)日：2024-09-24

申请号：US17379936

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shi-Ning Ju ,  Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Kuan-Lun Cheng ,  Guan-Lin Chen ,  Kuan-Ting Pan

IPC: H01L29/786 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66742

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, and a third semiconductor channel over the substrate and laterally offset from the second semiconductor channel. A first gate structure, a second gate structure, and a third gate structure are over and lateral surround the first, second, and third semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure, and a second inactive fin is between the second gate structure and the third gate structure. A bridge conductor layer is over the first, second, and third gate structures, and the first and second inactive fins. A dielectric plug extends from an upper surface of the second inactive fin, through the bridge conductor layer, to at least an upper surface of the bridge conductor layer.

公开(公告)号：US20240312990A1

公开(公告)日：2024-09-19

申请号：US18677372

申请日：2024-05-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chao-Shuo CHEN ,  Chia-Der Chang ,  Yi-Jing Lee

IPC: H01L27/088 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0924 ,  H01L21/31116 ,  H01L21/32135 ,  H01L27/0928

Abstract: A semiconductor device with an isolation structure and a method of fabricating the same are disclosed. The semiconductor device includes first and second fin structures disposed on a substrate and first and second pairs of gate structures disposed on the first and second fin structures. The first end surfaces of the first pair of gate structures face second end surfaces of the second pair of gate structure. The first and second end surfaces of the first and second pair of gate structures are in physical contact with first and second sidewalls of the isolation structure, respectively. The semiconductor device further includes an isolation structure interposed between the first and second pairs of gate structures. An aspect ratio of the isolation structure is smaller than a combined aspect ratio of the first pair of gate structures.

公开(公告)号：US20240312843A1

公开(公告)日：2024-09-19

申请号：US18184024

申请日：2023-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Ging Lin ,  Yi-Chun Chen ,  Jih-Jse Lin

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L27/0886

Abstract: A method includes forming a gate stack on a semiconductor region, wherein the semiconductor region is over a bulk semiconductor substrate. The gate stack is etched to form a first trench, wherein a plurality of protruding semiconductor fins are revealed to the first trench. The plurality of protruding semiconductor fins are etched to form a plurality of second trenches extending into the bulk semiconductor substrate. The plurality of second trenches are underlying and joined to the first trench. The plurality of second trenches include a first outmost trench having a first depth, a second outmost trench, and an inner trench between the first outmost trench and the second outmost trench. The inner trench has a second depth equal to or smaller than the first depth. A fin isolation region is formed to fill the first trench and the plurality of second trenches.

公开(公告)号：US12094784B2

公开(公告)日：2024-09-17

申请号：US18361501

申请日：2023-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chung-Ting Ko ,  Sung-En Lin ,  Chi On Chui

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/823481 ,  H01L21/02356 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a semiconductor fin over a substrate; forming an isolation feature adjacent semiconductor fin; recessing the isolation feature to form a recess; forming a metal-containing compound mask in the recess; depositing a stress layer over the metal-containing compound mask, such that the stress layer is in contact with a top surface of the metal-containing compound mask; and annealing the metal-containing compound mask when the stress layer is in contact with the top surface of the metal-containing compound mask.

公开(公告)号：US20240282670A1

公开(公告)日：2024-08-22

申请号：US18221696

申请日：2023-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Yang ,  Wonhyuk Hong ,  Myunghoon Jung ,  Jongjin Lee ,  Jaejik Baek ,  Kang-ill Seo

IPC: H01L23/48 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes: at least one transistor comprising source/drain regions and 1st gate structure; a contact isolation layer below the 1st gate structure; and a backside contact plug connected to at least one of the 1st source/drain regions, wherein the backside contact plug is formed below the 1st source/drain region and extended to a region below the 1st gate structure, and isolated from the 1st gate structure by the contact isolation layer.

公开(公告)号：US20240282636A1

公开(公告)日：2024-08-22

申请号：US18169928

申请日：2023-02-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hui Hung Kuo ,  Hsin Fu Lin ,  Hsin Heng Wang

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/56 ,  H01L29/06

CPC classification number: H01L21/823481 ,  H01L21/02617 ,  H01L21/31144 ,  H01L21/3213 ,  H01L21/56 ,  H01L29/0649

Abstract: Provided are device with stepped isolation regions and methods for fabricating the same. An exemplary method includes forming mask segments over a semiconductor material; etching the semiconductor material to form first trenches, wherein the first trenches have a first trench maximum width and a first trench depth; forming a coating in the first trenches, wherein the coating has a coating depth less than the first trench depth, and wherein uncovered portions of the semiconductor material extend from the coating to the patterned masks; performing an etch process to etch the mask segments and the uncovered portions of the semiconductor material to form second trenches over the first trenches, wherein the second trenches have a second minimum width greater than the first maximum width and a second depth less than the first depth; and removing the coating from the first trenches.