公开(公告)号：US06788580B2

公开(公告)日：2004-09-07

申请号：US10454630

申请日：2003-06-05

Applicant: Satoshi Takahashi

Inventor： Satoshi Takahashi

IPC: G11C1606

CPC classification number: G11C16/3463 ,  G11C16/3404 ,  G11C16/3413 ,  G11C16/3454 ,  G11C2216/18

Abstract: A nonvolatile semiconductor storage device includes a memory cell array and a reference cell providing a reference level with which data of the memory cell array is compared with so as to determine whether the data of the memory cell array is in an over-programmed state.

Abstract translation: 非易失性半导体存储装置包括存储单元阵列和提供与存储单元阵列的数据进行比较的参考电平的参考单元，以便确定存储单元阵列的数据是否处于过度编程状态。

公开(公告)号：US06744675B1

公开(公告)日：2004-06-01

申请号：US10305756

申请日：2002-11-26

Applicant: Wei Zheng ,  Mark W. Randolph

Inventor： Wei Zheng ,  Mark W. Randolph

IPC: G11C1600

CPC classification number: G11C16/3413 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3404

Abstract: In a non-volatile SONOS-type memory device having a charge storing layer disposed between top and bottom dielectric layers, a method of programming the memory device includes selectively storing charge in an upper portion of the charge storing layer. The method includes performing a channel hot electron injection procedure followed by a soft erase operation in which charge within a bottom portion of the first charging cell is removed. A verification procedure is performed to determine whether at least one charge storing cell is in a programmed state. The method provides a programmed cell in which the stored charge is disposed adjacent an upper portion of the cell near the top dielectric.

Abstract translation: 在具有设置在顶部和底部介电层之间的电荷存储层的非易失性SONOS型存储器件中，对存储器件进行编程的方法包括在电荷存储层的上部选择性地存储电荷。 该方法包括执行通道热电子注入程序，随后进行软擦除操作，其中去除第一充电单元的底部内的电荷。 执行验证过程以确定至少一个电荷存储单元是否处于编程状态。 该方法提供了一个编程单元，其中存储的电荷邻近靠近顶部电介质的单元的上部附近设置。

公开(公告)号：US20030206435A1

公开(公告)日：2003-11-06

申请号：US10454630

申请日：2003-06-05

Applicant: FUJITSU LIMITED

Inventor： Satoshi Takahashi

IPC: G11C011/15

CPC classification number: G11C16/3463 ,  G11C16/3404 ,  G11C16/3413 ,  G11C16/3454 ,  G11C2216/18

Abstract: A nonvolatile semiconductor storage device includes a memory cell array and a reference cell providing a reference level with which data of the memory cell array is compared with so as to determine whether the data of the memory cell array is in an over-programmed state.

Abstract translation: 非易失性半导体存储装置包括存储单元阵列和提供与存储单元阵列的数据进行比较的参考电平的参考单元，以便确定存储单元阵列的数据是否处于过度编程状态。

公开(公告)号：US06496417B1

公开(公告)日：2002-12-17

申请号：US09601089

申请日：2000-07-27

Applicant: Tzeng-Huei Shiau ,  Ray-Lin Wan ,  Han Sung Chen ,  Yu-Shen Lin ,  Wen-Pin Lu ,  Tso-Ming Chang

Inventor： Tzeng-Huei Shiau ,  Ray-Lin Wan ,  Han Sung Chen ,  Yu-Shen Lin ,  Wen-Pin Lu ,  Tso-Ming Chang

IPC: G11C1604

CPC classification number: G11C16/107 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3413 ,  G11C16/3445

Abstract: A method and an integrated circuit for performing a soft program after erase provides efficient convergence of over-erased floating gate memory cells disposed in bit lines. The soft program is applied to successive subject bit lines. The BLISP method includes selection of a selected bit line and applying the soft program to a subject bit line corresponding to the selected bit line. For integrated circuits having no defective bit lines, the subject bit lines comprise the selected bit lines. The BLISP method is adapted for low current consumption compared to bulk soft programming methods. In some embodiments, the integrated circuit includes defective bit lines. For these integrated circuits, the selection of the selected bit line includes indicating a bit line type corresponding to the selected bit line. The defective bit lines are logically replaced by redundant bit lines so that the soft program is applied to conforming selected bit lines and redundant bit lines corresponding to defective bit lines. The defective bit lines in the first memory array can be disabled during the soft program and replaced by corresponding redundant bit lines disposed in the second memory array, so that the soft program is not applied to the defective bit lines. By preventing application of the soft program to the defective bit lines, the BLISP method avoids consumption of excessive current that would otherwise be consumed by very low threshold voltage memory cells disposed on the defective bit lines. The excessive current would render the soft program method much less efficient.

Abstract translation: 用于在擦除之后执行软程序的方法和集成电路提供了布置在位线中的过擦除的浮动栅极存储单元的有效收敛。 软程序应用于连续的主题位线。 BLISP方法包括选择所选位线并将软程序应用于对应于所选位线的对象位线。 对于没有有缺陷的位线的集成电路，主题位线包括所选择的位线。 与批量软编程方法相比，BLISP方法适用于低电流消耗。 在一些实施例中，集成电路包括有缺陷的位线。 对于这些集成电路，选择的位线的选择包括指示对应于所选位线的位线类型。 有缺陷的位线在逻辑上被冗余位线替代，使得软程序被应用于对应于有缺陷位线的选定位线和冗余位线。 可以在软程序期间禁用第一存储器阵列中的有缺陷的位线，并且由位于第二存储器阵列中的对应的冗余位线替换第一存储器阵列中的有缺陷的位线，使得软程序不被施加到有缺陷的位线。 通过防止将软程序应用于有缺陷的位线，BLISP方法避免消耗过剩的电流，否则会由设置在有缺陷位线上的非常低的阈值电压存储单元消耗。 过度的电流将使软程序方法效率低得多。

公开(公告)号：US6130841A

公开(公告)日：2000-10-10

申请号：US432070

申请日：1999-11-02

Applicant: Toshihiro Tanaka ,  Masataka Kato ,  Osamu Tsuchiya ,  Toshiaki Nishimoto

Inventor： Toshihiro Tanaka ,  Masataka Kato ,  Osamu Tsuchiya ,  Toshiaki Nishimoto

IPC: G11C16/04 ,  G11C16/28 ,  G11C16/34 ,  G11C16/06

CPC classification number: G11C16/3413 ,  G11C16/0416 ,  G11C16/28 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3459

Abstract: After decreasing the threshold voltages of a plurality of memory cells collectively or selectively, the presence or absence of any memory cell of which the threshold voltage has dropped below a predetermined voltage verified collectively for each of memory cell groups connected to word line (low-threshold value verification) , and any memory cell of which the threshold voltage has excessively dropped is selectively written. Also, the well of each of memory cell is formed in the region of an element isolation layer for isolating it from the substrate of a memory apparatus, and a negative voltage is supplied to the memory well distributively with a positive voltage applied as a word line voltage, thus supplying them as erase operation voltages. The absolute value of the memory well voltage is set substantially equal to or lower than the word line voltage for the read operation. Sectors constituting each memory mat includes a sector (selected sector) selected for the erase operation with each word line thereof supplied with a positive voltage, a sector (non-selected sector) not selected for the erase operation with a word line voltage different from a memory well voltage, and further a sector (completely non-selected sector) not selected for the erase operation with a word line voltage equal to the voltage between a source and a drain of the memory cell.

Abstract translation: 在集体或选择性地降低多个存储器单元的阈值电压之后，存在或不存在阈值电压已经降低到连接到字线的每个存储器单元组（低阈值）下集中验证的预定电压以下的任何存储单元 值验证），并且选择性地写入阈值电压过度下降的任何存储单元。 此外，存储单元的阱形成在用于将其与存储装置的基板隔离的元件隔离层的区域中，并且以施加作为字线的正电压将负电压分配地提供给存储器 电压，从而将其提供为擦除操作电压。 存储器阱电压的绝对值被设定为基本上等于或低于读取操作的字线电压。 构成每个存储器垫的扇区包括为其擦除操作选择的扇区（选择的扇区），其每个字线被提供有正电压，未被选择用于擦除操作的扇区（未选择的扇区），字线电压不同于 存储器阱电压，以及未被选择用于具有等于存储器单元的源极和漏极之间的电压的字线电压的擦除操作的扇区（完全未选择的扇区）。

公开(公告)号：US5856945A

公开(公告)日：1999-01-05

申请号：US906198

申请日：1997-08-05

Applicant: Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

Inventor： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  H01L27/115 ,  G11C16/06

CPC classification number: G11C16/3409 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0416 ,  G11C16/34 ,  G11C16/3404 ,  G11C16/3413 ,  G11C16/3418 ,  H01L27/115 ,  G11C2216/20

Abstract: The present invention provides a method for preventing sub-threshold leakage in flash EPROM cells during Vt repair, read and verify operations. The present invention prevents sub-threshold leakage by either biasing the floating gate voltage of non-selected cells to a level that is less than the sources voltage. This biasing is achieved by controlling the voltages applied to such non-selected cells bitline and wordline voltages, or by floating the non-selected sourcelines to electrically disconnect the sourcelines of the non-selected cells. This method allows fast and accurate Vt repair of cells while avoiding Vt degradation of non-erased and repaired cells due to subthreshold current leakage, as well as reduced sub-threshold leakage during read and verify operations.

Abstract translation: 本发明提供一种在Vt修复，读取和验证操作期间防止闪存EPROM单元中的次阈值泄漏的方法。 本发明通过将未选择的单元的浮置栅极电压偏置到小于源极电压的水平来防止亚阈值泄漏。 通过控制施加到这种未选择的单元位线和字线电压的电压，或者通过浮动未选择的电源线来电连接未选择的单元的源极线来实现该偏置。 该方法允许快速且准确的Vt修复细胞，同时避免由于亚阈值电流泄漏而导致的未擦除和修复的细胞的Vt劣化，以及在读取和验证操作期间降低的亚阈值泄漏。

公开(公告)号：US5321699A

公开(公告)日：1994-06-14

申请号：US851286

申请日：1992-03-12

Applicant: Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

Inventor： Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

IPC: G11C11/56 ,  G11C16/34 ,  G11C29/50 ,  G01R31/28

CPC classification number: G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/3404 ,  G11C16/3413 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/3459 ,  G11C29/50 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/0403 ,  G11C2211/5621

Abstract: An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit lines and a comparator. A data-latch circuit is connected to the comparator, for latching a write-data supplied from a data input buffer. After desired cell transistors selected for programming in a selected block are once programmed, a write-verify operation is performed. The comparator compares the actual data read from one of the programmed cell transistors with the write-data, to verify its written state. The write-verify process checks the resulting threshold voltage for variations using first and second reference voltages defining the lower-limit and upper-limit of an allowable variation range. If the comparison results under employment of the first voltage shows that an irregularly written cell transistor remains with an insufficient threshold voltage which is so low as to fail to fall within the range, the write operation continues for the same cell transistor. If the comparison results under employment of the second voltage shows that an excess-written cell transistor remains, the block is rendered "protected" at least partially.

Abstract translation: EEPROM包括存储单元晶体管的阵列，其被分成每个包括串联连接的单元晶体管的NAND单元单元的单元块。 读出放大器连接到位线和比较器。 数据锁存电路连接到比较器，用于锁存从数据输入缓冲器提供的写入数据。 在所选择的块中选择用于编程的所需单元晶体管被一次编程之后，执行写验证操作。 比较器将从编程单元晶体管之一读取的实际数据与写入数据进行比较，以验证其写入状态。 写验证过程使用限定允许变化范围的下限和上限的第一和第二参考电压来检查所得到的阈值电压的变化。 如果使用第一电压的比较结果表明，不规则写入的单元晶体管保持不足阈值电压，其不足以落在该范围内，对于相同的单元晶体管，写操作继续进行。 如果在使用第二电压的情况下的比较结果表明剩余写入过多的单元晶体管，则该块至少部分地被“保护”。

公开(公告)号：US20190237149A1

公开(公告)日：2019-08-01

申请号：US16383486

申请日：2019-04-12

Applicant: SK hynix Inc.

Inventor： Ji Man HONG

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/3413 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3463 ,  G11C2211/563

Abstract: A semiconductor memory device and a method of operating the same are provided. The method of operating the semiconductor memory device includes determining a target word line coupled to an over-programmed memory cell, backing up data stored in memory cells coupled to the target word line in a second memory area, wherein the se second memory area is different from a first memory area where the memory cells coupled to the target word line are disposed, and applying a stepped-up read pass voltage to the target word line when a read operation is performed on a selected memory cell in a memory block coupled to the target word line, wherein the selected memory cell is different from the over-programmed memory cell. Therefore, the operation reliability of the semiconductor memory device is improved.

公开(公告)号：US20160071602A1

公开(公告)日：2016-03-10

申请号：US14945569

申请日：2015-11-19

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Yasuhiro Shiino ,  Eietsu Takahashi

IPC: G11C16/14 ,  G11C16/34 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C16/0483 ,  G11C11/5635 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/28 ,  G11C16/3404 ,  G11C16/3413 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3463 ,  G11C2211/5621

Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

Abstract translation: 非易失性半导体存储器件包括：控制电路，被配置为控制将非易失性存储器单元设置为非易失性存储单元的第一阈值电压分布状态的软编程操作。 当非易失性存储单元的特性处于第一状态时，控制电路通过将用于将非易失性存储单元设置为第一阈值电压分布状态的第一电压施加到第一字线来执行软编程操作，并且施加第二电压 高于第一个电压到第二个字线。 当非易失性存储单元的特性处于第二状态时，控制电路通过向第一字线施加等于或低于第一电压的第三电压并施加低于第二电压的第四电压来执行软编程操作 到第二个字线。

公开(公告)号：US09183924B2

公开(公告)日：2015-11-10

申请号：US14712939

申请日：2015-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Sang Lee ,  Moosung Kim ,  Kihwan Choi

IPC: G11C29/00 ,  G11C11/56 ,  G11C16/34 ,  G06F11/10

CPC classification number: G11C11/5635 ,  G06F11/1048 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/02 ,  G11C16/0483 ,  G11C16/3413 ,  G11C16/3436 ,  G11C16/3454 ,  G11C29/04 ,  G11C2029/0411 ,  G11C2211/5621

Abstract: Methods of operating nonvolatile memory devices may include identifying one or more multi-bit nonvolatile memory cells in a nonvolatile memory device that have undergone unintentional programming from an erased state to an at least partially programmed state. Errors generated during an operation to program a first plurality of multi-bit nonvolatile memory cells may be detected by performing a plurality of reading operations to generate error detection data and then decoding the error detection data to identify specific cells having errors. A programmed first plurality of multi-bit nonvolatile memory cells and a force-bit data vector, which was modified during the program operation, may be read to support error detection. This data, along with data read from a page buffer associated with the first plurality of multi-bit nonvolatile memory cells, may then be decoded to identify which of the first plurality of multi-bit nonvolatile memory cells are unintentionally programmed cells.