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    Method for preparing compound semiconductor substrate
    11.
    发明授权
    Method for preparing compound semiconductor substrate 有权
    化合物半导体衬底的制备方法

    公开(公告)号：US07816241B2

    公开(公告)日：2010-10-19

    申请号：US12177917

    申请日：2008-07-23

    Applicant: Ho-Jun Lee ,  Yong-Jin Kim ,  Dong-Kun Lee ,  Doo-Soo Kim ,  Ji-Hoon Kim

    Inventor： Ho-Jun Lee ,  Yong-Jin Kim ,  Dong-Kun Lee ,  Doo-Soo Kim ,  Ji-Hoon Kim

    IPC: H01L21/28

    CPC classification number: H01L21/0254 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/02664

    Abstract: Provided is a method for preparing a compound semiconductor substrate. The method includes coating a plurality of spherical balls on a substrate, growing a compound semiconductor epitaxial layer on the substrate coated with the spherical balls while allowing voids to be formed under the spherical balls, and cooling the substrate on which the compound semiconductor epitaxial layer is grown so that the substrate and the compound semiconductor epitaxial layer are self-separated along the voids. The spherical ball treatment can reduce dislocation generations. In addition, because the substrate and the compound semiconductor epitaxial layer are separated through the self-separation, there is no need for laser lift-off process.

    Abstract translation: 提供了一种制备化合物半导体衬底的方法。 该方法包括在基板上涂覆多个球形球，在涂覆有球形球的基材上生长化合物半导体外延层，同时允许在球形球下方形成空隙，并且冷却其上化合物半导体外延层为 生长，使得衬底和化合物半导体外延层沿着空隙自我分离。 球形球处理可以减少错位几代。 此外，由于基板和化合物半导体外延层通过自分离分离，因此不需要激光剥离处理。

    High Quality Single Crystal and Method of Growing the Same
    12.
    发明申请
    High Quality Single Crystal and Method of Growing the Same 审中-公开
    高品质单晶及其生长方法

    公开(公告)号：US20090272948A1

    公开(公告)日：2009-11-05

    申请号：US12166366

    申请日：2008-07-02

    Applicant: Hyon-Jong CHO

    Inventor： Hyon-Jong CHO

    IPC: H01B1/02 ,  C01B33/02 ,  C01B25/00 ,  C01B35/12 ,  C01G33/00 ,  C01G35/00

    CPC classification number: C30B29/22 ,  C30B11/003 ,  C30B13/16 ,  C30B15/14 ,  C30B17/00 ,  C30B29/06 ,  C30B29/08 ,  C30B29/20 ,  C30B29/42 ,  Y10T117/1032 ,  Y10T117/1068

    Abstract: Disclosed is a method of growing a single crystal from a melt contained in a crucible. The method includes the step of making the temperature of a melt increase gradually to a maximum point and then decrease gradually along the axis parallel to the lengthwise direction of the single crystal from the interface of the single crystal and the melt to the bottom of the crucible. The increasing temperature of the melt is kept to preferably have a greater temperature gradient than the decreasing temperature thereof. Preferably, the axis is set to pass through the center of the single crystal. Preferably, the convection of the inner region of the melt is made smaller than that of the outer region thereof.

    Abstract translation: 公开了从包含在坩埚中的熔体中生长单晶的方法。 该方法包括使熔体的温度逐渐升高到最大点，然后沿着与单晶长度方向平行的轴从晶体和熔体的界面到坩埚的底部逐渐减小的步骤 。 保持熔体的温度升高优选具有比其降低的温度更大的温度梯度。 优选地，轴被设定为穿过单晶的中心。 优选地，熔体的内部区域的对流被制成小于其外部区域的对流。

    Method of fabricating nano SOI wafer and nano SOI wafer fabricated by the same
    15.
    发明授权
    Method of fabricating nano SOI wafer and nano SOI wafer fabricated by the same 有权
    制造纳米SOI晶片和纳米SOI晶片的方法

    公开(公告)号：US07338882B2

    公开(公告)日：2008-03-04

    申请号：US11084033

    申请日：2005-03-21

    Applicant: Jea-Gun Park ,  Gon-Sub Lee ,  Sang-Hee Lee

    Inventor： Jea-Gun Park ,  Gon-Sub Lee ,  Sang-Hee Lee

    IPC: H01L21/46 ,  H01L21/302

    CPC classification number: H01L21/76254 ,  Y10S438/959

    Abstract: A method of fabricating a nano silicon on insulator (SOI) wafer having an excellent thickness evenness without performing a chemical mechanical polishing (CMP) and a wafer fabricated by the same are provided. The provided method includes preparing a bond wafer and a base wafer, and forming a dielectric on at least on surface of the bond wafer. Thereafter, an impurity ion implantation unit is formed by implanting impurity ions into the bond wafer to a predetermined depth from the surface of the bond wafer at a low voltage. The dielectric of the bond wafer and the base wafer contact each other in order to be bonded. Next, a thermal process of low temperature is performed to cleave the impurity ion implantation unit of the bond wafer. In addition, the cleaved surface of the bond wafer bonded to the base wafer is etched to form a nano scale device region. Here, the cleaved surface may be etched by performing a hydrogen surface process and a wet etching.

    Abstract translation: 提供了不进行化学机械抛光（CMP）和由其制造的晶片的制造具有优异的厚度均匀性的纳米绝缘体（SOI）晶片的方法。 所提供的方法包括制备接合晶片和基底晶片，并且在接合晶片的至少一个表面上形成电介质。 此后，通过以低电压将杂质离子注入接合晶片到接合晶片的表面至预定深度来形成杂质离子注入单元。 接合晶片和基底晶片的电介质彼此接触以便结合。 接下来，进行低温的热处理，以切割接合晶片的杂质离子注入单元。 此外，蚀刻结合到基底晶片的接合晶片的切割表面以形成纳米级器件区域。 这里，可以通过进行氢表面处理和湿蚀刻来蚀刻裂开的表面。

    Apparatus and method for slicing an ingot
    16.
    发明授权
    Apparatus and method for slicing an ingot 有权
    用于切割锭的装置和方法

    公开(公告)号：US07261099B2

    公开(公告)日：2007-08-28

    申请号：US11256331

    申请日：2005-10-21

    Applicant: Eunsang Ji ,  Kyungmoo Lee

    Inventor： Eunsang Ji ,  Kyungmoo Lee

    IPC: B28D1/06

    CPC classification number: B24B27/0633 ,  B28D5/0064 ,  B28D5/007 ,  B28D5/045 ,  Y02P70/179 ,  Y10T83/9292

    Abstract: A method for slicing an ingot may improve nanotopography at a surface of a wafer. In the method, an ingot is sliced into a plurality of wafers via a slurry while slurry is supplied to a moving wire. A first wire to form a first slicing portion at the wafer firstly slices one side of the ingot. A second wire secondly slices the remaining portion of the ingot to form a second slicing portion continued from the first slicing portion, wherein the first wire has a smaller diameter than that of the second wire.

    Abstract translation: 用于切割锭的方法可以改善晶片表面的纳米形貌。 在该方法中，通过浆料将晶锭切割成多个晶片，同时将浆料供给到移动金属丝。 在晶片上形成第一切割部分的第一线首先切割锭的一侧。 第二丝线二次切割锭的剩余部分以形成从第一切片部分继续的第二切片部分，其中第一丝线具有比第二丝线小的直径。

    Method for producing high quality silicon single crystal ingot and silicon single crystal wafer made thereby
    17.
    发明申请
    Method for producing high quality silicon single crystal ingot and silicon single crystal wafer made thereby 有权
    由此制造高品质硅单晶锭和硅单晶晶片的方法

    公开(公告)号：US20070151505A1

    公开(公告)日：2007-07-05

    申请号：US11643201

    申请日：2006-12-21

    Applicant: Hyon-Jong Cho

    Inventor： Hyon-Jong Cho

    IPC: C30B5/00 ,  C30B15/00 ,  C30B19/00 ,  C30B21/06

    CPC classification number: C30B29/06 ,  C30B15/14 ,  C30B15/203 ,  Y10T117/1068 ,  Y10T117/1072 ,  Y10T117/1088

    Abstract: In a method for producing a high quality silicon single crystal by the Czochralski method, a lower portion of a solid-liquid interface of a single crystal growth is divided into a central part and a circumferential part, and the temperature gradient of the central part and the temperature gradient of the circumferential part are separately controlled. When a silicon melt located at a lower portion of a solid-liquid interface of a single crystal growth is divided into a central part melt and a circumferential part melt, the method controls the temperature gradient of the central part melt by directly controlling the temperature distribution of a melt and indirectly controls the temperature gradient of the circumferential part melt by controlling the temperature gradient of the single crystal, thereby effectively controlling the overall temperature distribution of the melt, thus producing a high quality single crystal ingot free of defects with a high growth velocity.

    Abstract translation: 在通过切克劳斯基法生产高品质硅单晶的方法中，单晶生长的固液界面的下部被分成中心部分和周边部分，中心部分和 圆周部分的温度梯度被单独控制。 当位于单晶生长的固 - 液界面的下部的硅熔体被分成中心部分熔体和圆周部分熔化时，该方法通过直接控制温度分布来控制中心熔体的温度梯度 并通过控制单晶的温度梯度来间接地控制圆周部分熔体的温度梯度，从而有效地控制熔体的总体温度分布，从而产生没有高生长缺陷的高质量单晶锭 速度。

    Nitride semiconductor device and method of manufacturing the same
    18.
    发明申请
    Nitride semiconductor device and method of manufacturing the same 有权
    氮化物半导体器件及其制造方法

    公开(公告)号：US20050199886A1

    公开(公告)日：2005-09-15

    申请号：US11074413

    申请日：2005-03-08

    Applicant: Gyu-Chul Yi ,  Sung An ,  Yong Kim

    Inventor： Gyu-Chul Yi ,  Sung An ,  Yong Kim

    IPC: C23C16/34 ,  C23C16/40 ,  H01L21/205 ,  H01L27/15 ,  H01L29/04 ,  H01L29/10 ,  H01L29/26 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/12 ,  H01L31/20 ,  H01L33/00

    CPC classification number: H01L33/007 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02447 ,  H01L21/02472 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02645 ,  H01L33/12 ,  Y10S977/759

    Abstract: Provided are a nitride semiconductor device and method of manufacturing the same. In the method, semiconductor nanorods are vertically grown on a substrate, and then a nitride semiconductor thin film is deposited on the substrate having the semiconductor nanorods. Accordingly, a high-quality nitride semiconductor thin film can be deposited on a variety of inexpensive, large-sized substrates. Also, because the nitride semiconductor thin film containing the semiconductor nanorods can easily emit light through openings between the nanorods, internal scattering can be greatly reduced. Thus, the nitride semiconductor thin film can be usefully employed in optical devices such as light emitting diodes and electronic devices.

    Abstract translation: 提供一种氮化物半导体器件及其制造方法。 在该方法中，半导体纳米棒在衬底上垂直生长，然后在具有半导体纳米棒的衬底上沉积氮化物半导体薄膜。 因此，可以在各种廉价的大尺寸基板上沉积高质量的氮化物半导体薄膜。 此外，由于含有半导体纳米棒的氮化物半导体薄膜可以容易地通过纳米棒之间的开口发光，因此可以大大降低内部散射。 因此，氮化物半导体薄膜可以有效地用于诸如发光二极管和电子器件的光学器件中。

    Method of fabricating nano SOI wafer and nano SOI wafer fabricated by the same
    19.
    发明申请
    Method of fabricating nano SOI wafer and nano SOI wafer fabricated by the same 有权
    制造纳米SOI晶片和纳米SOI晶片的方法

    公开(公告)号：US20050164435A1

    公开(公告)日：2005-07-28

    申请号：US11084033

    申请日：2005-03-21

    Applicant: Jea-Gun Park ,  Gon-Sub Lee ,  Sang-Hee Lee

    Inventor： Jea-Gun Park ,  Gon-Sub Lee ,  Sang-Hee Lee

    IPC: H01L21/20 ,  H01L21/02 ,  H01L21/265 ,  H01L21/762 ,  H01L27/12 ,  H01L21/00 ,  H01L21/30 ,  H01L21/46 ,  H01L21/84

    CPC classification number: H01L21/76254 ,  Y10S438/959

    Abstract: A method of fabricating a nano silicon on insulator (SOI) wafer having an excellent thickness evenness without performing a chemical mechanical polishing (CMP) and a wafer fabricated by the same are provided. The provided method includes preparing a bond wafer and a base wafer, and forming a dielectric on at least on surface of the bond wafer. Thereafter, an impurity ion implantation unit is formed by implanting impurity ions into the bond wafer to a predetermined depth from the surface of the bond wafer at a low voltage. The dielectric of the bond wafer and the base wafer contact each other in order to be bonded. Next, a thermal process of low temperature is performed to cleave the impurity ion implantation unit of the bond wafer. In addition, the cleaved surface of the bond wafer bonded to the base wafer is etched to form a nano scale device region. Here, the cleaved surface may be etched by performing a hydrogen surface process and a wet etching.

    Abstract translation: 提供了不进行化学机械抛光（CMP）和由其制造的晶片的制造具有优异的厚度均匀性的纳米绝缘体（SOI）晶片的方法。 所提供的方法包括制备接合晶片和基底晶片，并且在接合晶片的至少一个表面上形成电介质。 此后，通过以低电压将杂质离子注入接合晶片到接合晶片的表面至预定深度来形成杂质离子注入单元。 接合晶片和基底晶片的电介质彼此接触以便结合。 接下来，进行低温的热处理，以切割接合晶片的杂质离子注入单元。 此外，蚀刻结合到基底晶片的接合晶片的切割表面以形成纳米级器件区域。 这里，可以通过进行氢表面处理和湿蚀刻来蚀刻裂开的表面。

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