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    SILICON AND SILICON GERMANIUM NANOWIRE FORMATION
    11.
    发明申请
    SILICON AND SILICON GERMANIUM NANOWIRE FORMATION 有权
    硅和硅锗纳米线形成

    公开(公告)号：US20150053928A1

    公开(公告)日：2015-02-26

    申请号：US13971239

    申请日：2013-08-20

    Applicant: Taiwan Semiconductor Manufacturing Company Limited

    Inventor： Kuo-Cheng Ching ,  Carlos H. Diaz ,  Jean-Pierre Colinge

    IPC: H01L29/775 ,  H01L21/8238

    CPC classification number: H01L21/823821 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7853 ,  H01L29/78696

    Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.

    Abstract translation: 其中，提供了一种或半导体布置，以及用于形成这种半导体布置的技术。 例如，使用一个或多个硅和硅锗堆叠来形成包括锗纳米线通道的PMOS晶体管和包括硅纳米线通道的NMOS晶体管。 在一个示例中，第一硅和硅锗堆叠被氧化以将硅转化为氧化硅区域，其被去除以形成用于PMOS晶体管的锗纳米线通道。 在另一示例中，去除第二硅和硅锗叠层内的硅层和锗层以形成用于NMOS晶体管的硅纳米线通道。 具有锗纳米线通道的PMOS晶体管和具有硅纳米线通道的NMOS晶体管被形成为单个制造工艺的一部分。

    SEMICONDUCTOR ARRANGEMENT WITH SUBSTRATE ISOLATION
    12.
    发明申请
    SEMICONDUCTOR ARRANGEMENT WITH SUBSTRATE ISOLATION 有权
    半导体布置与基片隔离

    公开(公告)号：US20140312432A1

    公开(公告)日：2014-10-23

    申请号：US14326746

    申请日：2014-07-09

    Applicant: Taiwan Semiconductor Manufacturing Company Limited

    Inventor： Kuo-Cheng Ching ,  Ching-Wei Tsai ,  Chih-Hao Wang ,  Carlos H. Diaz

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/66795 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/785 ,  H01L29/78696

    Abstract: One or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a channel, such as an un-doped channel, over a substrate. The semiconductor arrangement comprises a gate, such as a gate-all-around structure gate, around the channel. The semiconductor arrangement comprises an isolation structure, such as a silicon germanium oxide structure, between the gate and the substrate. The isolation structure blocks current leakage into the substrate. Because the semiconductor arrangement comprises the isolation structure, the channel can be left un-doped, which improves electron mobility and decreases gate capacitance.

    Abstract translation: 提供了一种或多种用于形成这种半导体布置的半导体布置和技术。 半导体装置包括在衬底上的通道，例如未掺杂沟道。 半导体装置包括围绕通道的门，例如栅极全周围结构栅极。 半导体装置包括在栅极和衬底之间的隔离结构，例如硅锗氧化物结构。 隔离结构阻止电流泄漏到基板中。 由于半导体装置包括隔离结构，通道可以保留未掺杂，这改善了电子迁移率并降低了栅极电容。

    Semiconductor arrangement and method of manufacture
    14.
    发明授权
    Semiconductor arrangement and method of manufacture 有权

    公开(公告)号：US11024545B2

    公开(公告)日：2021-06-01

    申请号：US16359245

    申请日：2019-03-20

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

    Inventor： Kuo-Cheng Ching ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Chung-Wei Hsu

    IPC: H01L21/8234 ,  H01L29/51 ,  H01L29/49 ,  H01L27/088 ,  H01L29/66

    Abstract: A method for forming a semiconductor arrangement comprises forming a first fin in a semiconductor layer. A first gate dielectric layer includes a first high-k material is formed over the first fin. A first sacrificial gate electrode is formed over the first fin. A dielectric layer is formed adjacent the first sacrificial gate electrode and over the first fin. The first sacrificial gate electrode is removed to define a first gate cavity in the dielectric layer. A second gate dielectric layer including a second dielectric material different than the first high-k material is formed over the first gate dielectric layer in the first gate cavity. A first gate electrode is formed in the first gate cavity over the second gate dielectric layer.

    Silicon and silicon germanium nanowire formation
    19.
    发明授权
    Silicon and silicon germanium nanowire formation 有权
    硅和硅锗纳米线形成

    公开(公告)号：US09184269B2

    公开(公告)日：2015-11-10

    申请号：US13971239

    申请日：2013-08-20

    Applicant: Taiwan Semiconductor Manufacturing Company Limited

    Inventor： Kuo-Cheng Ching ,  Carlos H. Diaz ,  Jean-Pierre Colinge

    IPC: H01L21/8234 ,  H01L29/775 ,  H01L21/8238 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/06

    CPC classification number: H01L21/823821 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7853 ,  H01L29/78696

    Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.

    Abstract translation: 其中，提供了一种或半导体布置，以及用于形成这种半导体布置的技术。 例如，使用一个或多个硅和硅锗堆叠来形成包括锗纳米线通道的PMOS晶体管和包括硅纳米线通道的NMOS晶体管。 在一个示例中，第一硅和硅锗堆叠被氧化以将硅转化为氧化硅区域，其被去除以形成用于PMOS晶体管的锗纳米线通道。 在另一示例中，去除第二硅和硅锗叠层内的硅层和锗层以形成用于NMOS晶体管的硅纳米线通道。 具有锗纳米线通道的PMOS晶体管和具有硅纳米线通道的NMOS晶体管被形成为单个制造工艺的一部分。

    SEMICONDUCTOR DEVICE AND FORMATION THEREOF
    20.
    发明申请
    SEMICONDUCTOR DEVICE AND FORMATION THEREOF 有权
    半导体器件及其形成

    公开(公告)号：US20150236114A1

    公开(公告)日：2015-08-20

    申请号：US14181800

    申请日：2014-02-17

    Applicant: Taiwan Semiconductor Manufacturing Company Limited

    Inventor： Kuo-Cheng Ching ,  Guan-Lin Chen ,  Chao-Hsiung Wang ,  Chi-Wen Liu

    IPC: H01L29/51 ,  H01L29/78 ,  H01L29/40

    CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795

    Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a barrier including carbon over a fin, the fin including a doped region. The semiconductor device includes an epitaxial (Epi) cap over the barrier, the Epi cap including phosphorus. The barrier inhibits phosphorus diffusion from the Epi cap into the fin as compared to a device that lacks such a barrier. The inhibition of the phosphorus diffusion reduces a short channel effect, thus improving the semiconductor device function.

    Abstract translation: 本文提供半导体器件和形成方法。 半导体器件包括在鳍上方包括碳的势垒，所述鳍包括掺杂区。 半导体器件包括在屏障上的外延（Epi）帽，Epi帽包括磷。 与不具有这种屏障的装置相比，阻挡层阻止磷从Epi帽扩散到鳍中。 磷扩散的抑制减小了沟道效应，从而提高了半导体器件的功能。

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