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公开(公告)号:US20230068279A1
公开(公告)日:2023-03-02
申请号:US17461536
申请日:2021-08-30
发明人: Shih-Yao Lin , Hsiao Wen Lee , Ming-Ching Chang
IPC分类号: H01L29/423 , H01L29/786 , H01L29/06 , H01L29/66 , H01L21/8234
摘要: A semiconductor device includes an active gate structure extending along a first lateral direction. The semiconductor device includes an inactive gate structure also extending along the first lateral direction. The semiconductor device includes a first epitaxial structure disposed between the active gate structure and the inactive gate structure along a second lateral direction perpendicular to the first lateral direction. The active gate structure wraps around each of a plurality of channel layers that extend along the second direction, and the inactive gate structure straddles a semiconductor cladding layer that continuously extends along a first sidewall of the first epitaxial structure and across the plurality of channel layers.
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公开(公告)号:US20230065476A1
公开(公告)日:2023-03-02
申请号:US17461039
申请日:2021-08-30
发明人: Shih-Yao Lin , Hsiao Wen Lee , Chih-Han Lin
IPC分类号: H01L29/423 , H01L29/66 , H01L21/8234 , H01L29/786
摘要: A method for making a semiconductor device includes forming a fin structure that extends along a first direction and comprises a plurality of sacrificial layers and a plurality of channel layers alternately stacked on top of one another. The method includes forming a dummy gate structure, over the fin structure, that extends along a second direction perpendicular to the first direction. The method includes forming a gate spacer extending along respective upper sidewall portions of the dummy gate structure, thereby defining a first distance between a bottom surface of the gate spacer and a top surface of a topmost one of the plurality of channel layers. The first distance is either zero or similar to a second distance that separates neighboring ones of the plurality of channel layers.
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公开(公告)号:US20230063087A1
公开(公告)日:2023-03-02
申请号:US17460075
申请日:2021-08-27
发明人: Shih-Yao Lin , Chen-Ping Chen , Chieh-Ning Feng , Hsiao Wen Lee , Chih-Han Lin
IPC分类号: H01L27/092 , H01L29/06 , H01L29/423 , H01L29/786 , H01L21/02 , H01L21/8238 , H01L29/66
摘要: A method includes forming a first, second, third, fourth, fifth, and sixth fin structure. The second fin structure is separated from each of the first and third fin structures by a first distance, the fifth fin structure is separated from each of the fourth and sixth fin structures by the first distance, and the third fin structure is separated from the fourth fin structure by a second distance greater than the first distance. The method includes forming a first dummy gate structure overlaying the first through third fin structures, and a second dummy gate structure overlaying the fourth through sixth fin structures; forming a number of source/drain structures that are coupled to the first, second, third, fourth, fifth, and sixth fin structures, respectively; and replacing the third fin structure with a first dielectric structure, and replacing the fourth fin structure with a second dielectric structure.
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公开(公告)号:US11562118B2
公开(公告)日:2023-01-24
申请号:US17140701
申请日:2021-01-04
发明人: Ching Hsu , Shih-Yao Lin , Yi-Lin Chuang
IPC分类号: G06F30/398 , G06F30/392 , G06N5/04 , G06N20/00
摘要: A method includes: training a machine learning model with a plurality of electronic circuit placement layouts; predicting, by the machine learning model, fix rates of design rule check (DRC) violations of a new electronic circuit placement layout; identifying hard-to-fix (HTF) DRC violations among the DRC violations based on the fix rates of the DRC violations of the new electronic circuit placement layout; and fixing, by an engineering change order (ECO) tool, the DRC violations.
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公开(公告)号:US20220302276A1
公开(公告)日:2022-09-22
申请号:US17834614
申请日:2022-06-07
发明人: Shih-Yao Lin , Chih-Han Lin , Hsiao Wen Lee
IPC分类号: H01L29/423 , H01L29/06 , H01L29/66 , H01L29/786 , H01L29/78
摘要: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.
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公开(公告)号:US12040359B2
公开(公告)日:2024-07-16
申请号:US17460204
申请日:2021-08-28
发明人: Shih-Yao Lin , Hsiao Wen Lee , Chao-Cheng Chen
IPC分类号: H01L29/423 , H01L21/762 , H01L21/8234 , H01L29/06 , H01L29/08 , H01L29/66 , H01L29/786
CPC分类号: H01L29/0847 , H01L29/0653 , H01L29/42392 , H01L29/66545 , H01L29/66553 , H01L29/66742 , H01L29/78696
摘要: A semiconductor device includes a plurality of channel layers vertically spaced from one another. The semiconductor device includes a gate structure wrapping around each of the plurality of channel layers. The semiconductor device includes an epitaxial structure electrically coupled to the plurality of channel layers. The epitaxial structure contacts a sidewall, a portion of a top surface, and a portion of a bottom surface of each of the plurality of channel layers.
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公开(公告)号:US20240234540A1
公开(公告)日:2024-07-11
申请号:US18609982
申请日:2024-03-19
发明人: Shih-Yao Lin , Hsiaowen Lee , Yu-Shan Cheng , Chao-Cheng Chen
IPC分类号: H01L29/66 , H01L21/764 , H01L29/06 , H01L29/423 , H01L29/786
CPC分类号: H01L29/6653 , H01L21/764 , H01L29/0665 , H01L29/42392 , H01L29/6656 , H01L29/78696
摘要: A method for fabricating semiconductor devices includes forming a channel structure over a substrate and along a first lateral direction; forming a gate structure extending along a second lateral direction and straddling a portion of the channel structure; forming a gate spacer along a side of the gate structure, the gate spacer having a lateral portion and a vertical portion; growing an epitaxial structure over the channel structure; and forming an air gap within the gate spacer. The air gap is entirely above the epitaxial structure and vertically separated from the epitaxial structure by the lateral portion of the gate spacer.
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公开(公告)号:US11923440B2
公开(公告)日:2024-03-05
申请号:US17873978
申请日:2022-07-26
发明人: Shih-Yao Lin , Chen-Ping Chen , Kuei-Yu Kao , Hsiao Wen Lee , Chih-Han Lin
IPC分类号: H01L29/94 , H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/66 , H01L29/76 , H01L29/78
CPC分类号: H01L29/6681 , H01L21/823431 , H01L21/823481 , H01L27/0886 , H01L29/0649 , H01L29/66545 , H01L29/785
摘要: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.
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公开(公告)号:US11908746B2
公开(公告)日:2024-02-20
申请号:US17460213
申请日:2021-08-28
发明人: Kuei-Yu Kao , Chao-Cheng Chen , Chih-Han Lin , Chen-Ping Chen , Ming-Ching Chang , Shih-Yao Lin , Chih-Chung Chiu
IPC分类号: H01L21/8234 , H01L29/423 , H01L29/66 , H01L29/786 , H01L29/06
CPC分类号: H01L21/823468 , H01L21/823431 , H01L29/0673 , H01L29/42392 , H01L29/6656 , H01L29/66545 , H01L29/66742 , H01L29/78618
摘要: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.
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公开(公告)号:US11856744B2
公开(公告)日:2023-12-26
申请号:US17460101
申请日:2021-08-27
发明人: Shih-Yao Lin , Hsiao Wen Lee , Chih-Han Lin
IPC分类号: H10B10/00 , H01L27/092 , H01L29/08 , H01L29/66 , H01L21/8238 , H01L29/417
CPC分类号: H10B10/12 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L27/0924 , H01L29/0847 , H01L29/41791 , H01L29/6681
摘要: A semiconductor device includes a first semiconductor fin extending along a first direction. The semiconductor device includes a second semiconductor fin also extending along the first direction. The semiconductor device includes a dielectric fin disposed between the first and second semiconductor fins, wherein the dielectric fin also extends along the first direction. The semiconductor device includes a gate structure extending along a second direction perpendicular to the first direction, the gate structure comprising a first portion and a second portion. A top surface of the dielectric fin is vertically above respective top surfaces of the first and second semiconductor fins. The first portion and the second portion are electrically isolated by the dielectric fin. The first portion of the gate structure overlays an edge portion of the first semiconductor fin, and the second portion of the gate structure overlays a non-edge portion of the second semiconductor fin.
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