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公开(公告)号：US20160225780A1
公开(公告)日：2016-08-04
申请号：US15061762
申请日：2016-03-04
发明人： Chia-Ta Hsieh , Po-Wei Liu , Yong-Shiuan Tsair , Chieh-Fei Chiu
IPC分类号： H01L27/115
CPC分类号： H01L27/11524 , H01L21/28008 , H01L21/28273 , H01L27/11521 , H01L27/11529 , H01L27/11548 , H01L29/66825 , H01L29/78
摘要： A method includes forming a first pad oxide layer and a second pad oxide layer over a first active region and a second active region, respectively, of a semiconductor substrate, forming a dielectric protection layer overlapping the first pad oxide layer, removing the second pad oxide layer, and forming a floating gate dielectric over the second active region. A floating gate layer is then formed to include a first portion over the dielectric protection layer, and a second portion over the floating gate dielectric. A planarization is performed on the first portion and the second portion of the floating gate layer. A blocking layer, a control gate layer, and a hard mask layer are formed over the second portion of the floating gate layer. The hard mask layer, the control gate layer, and the blocking layer are patterned to form a gate stack for a flash memory cell.
摘要翻译： 一种方法包括分别在半导体衬底的第一有源区和第二有源区上形成第一衬垫氧化物层和第二衬垫氧化物层，形成与第一衬垫氧化物层重叠的介电保护层，去除第二衬垫氧化物 层，并且在第二有源区上形成浮栅电介质。 然后形成浮栅层以包括介电保护层上的第一部分，以及浮置栅极电介质上的第二部分。 在浮栅层的第一部分和第二部分上进行平坦化。 在浮置栅极层的第二部分上形成阻挡层，控制栅极层和硬掩模层。 对硬掩模层，控制栅层和阻挡层进行图案化以形成用于闪存单元的栅叠层。
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公开(公告)号：US11785770B2
公开(公告)日：2023-10-10
申请号：US18079047
申请日：2022-12-12
发明人： Wen-Tuo Huang , Ping-Cheng Li , Hung-Ling Shih , Po-Wei Liu , Yu-Ling Hsu , Yong-Shiuan Tsair , Chia-Sheng Lin , Shih Kuang Yang
IPC分类号： H01L21/768 , H10B41/30 , H01L21/28 , H01L23/522 , H01L23/528 , H01L23/532 , H01L29/40 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/788
CPC分类号： H10B41/30 , H01L21/76802 , H01L21/76877 , H01L23/528 , H01L23/5226 , H01L23/53271 , H01L29/401 , H01L29/40114 , H01L29/42328 , H01L29/4916 , H01L29/66825 , H01L29/788
摘要： Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.
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公开(公告)号：US20220352308A1
公开(公告)日：2022-11-03
申请号：US17867787
申请日：2022-07-19
发明人： Yu-Hung Cheng , Cheng-Ta Wu , Po-Wei Liu , Yeur-Luen Tu , Yu-Chun Chang
IPC分类号： H01L29/06 , H01L21/762 , H01L21/763
摘要： In some embodiments, the present disclosure relates to an integrated chip that includes a semiconductor device, a polysilicon isolation structure, and a first and second insulator liner. The semiconductor device is disposed on a frontside of a substrate. The polysilicon isolation structure continuously surrounds the semiconductor device and extends from the frontside of the substrate towards a backside of the substrate. The first insulator liner and second insulator liner respectively surround a first outermost sidewall and a second outermost sidewall of the polysilicon isolation structure. The substrate includes a monocrystalline facet arranged between the first and second insulator liners. A top of the monocrystalline facet is above bottommost surfaces of the polysilicon isolation structure, the first insulator liner, and the second insulator liner.
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公开(公告)号：US20150214237A1
公开(公告)日：2015-07-30
申请号：US14166431
申请日：2014-01-28
发明人： Chia-Ta Hsieh , Po-Wei Liu , Yong-Shiuan Tsair , Chieh-Fei Chiu
IPC分类号： H01L27/115 , H01L21/28
CPC分类号： H01L27/11524 , H01L21/28008 , H01L21/28273 , H01L27/11521 , H01L27/11529 , H01L27/11548 , H01L29/66825 , H01L29/78
摘要： A method includes forming a first pad oxide layer and a second pad oxide layer over a first active region and a second active region, respectively, of a semiconductor substrate, forming a dielectric protection layer overlapping the first pad oxide layer, removing the second pad oxide layer, and forming a floating gate dielectric over the second active region. A floating gate layer is then formed to include a first portion over the dielectric protection layer, and a second portion over the floating gate dielectric. A planarization is performed on the first portion and the second portion of the floating gate layer. A blocking layer, a control gate layer, and a hard mask layer are formed over the second portion of the floating gate layer. The hard mask layer, the control gate layer, and the blocking layer are patterned to form a gate stack for a flash memory cell.
摘要翻译： 一种方法包括分别在半导体衬底的第一有源区和第二有源区上形成第一衬垫氧化物层和第二衬垫氧化物层，形成与第一衬垫氧化物层重叠的介电保护层，去除第二衬垫氧化物 层，并且在第二有源区上形成浮栅电介质。 然后形成浮栅层以包括介电保护层上的第一部分，以及浮置栅极电介质上的第二部分。 在浮栅层的第一部分和第二部分上进行平坦化。 在浮置栅极层的第二部分上形成阻挡层，控制栅极层和硬掩模层。 对硬掩模层，控制栅层和阻挡层进行图案化以形成用于闪存单元的栅叠层。
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15.发明授权公开(公告)号：US08890232B2
公开(公告)日：2014-11-18
申请号：US14176968
申请日：2014-02-10
发明人： Yong-Shiuan Tsair , Wen-Ting Chu , Po-Wei Liu , Wen-Tuo Huang , Yu-Hsiang Yang , Chieh-Fei Chiu , Yu-Ling Hsu
IPC分类号： H01L29/788 , H01L27/115 , H01L29/423 , H01L21/28
CPC分类号： H01L21/28273 , H01L27/11517 , H01L29/42328 , H01L29/7881
摘要： Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided.
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公开(公告)号：US20240355393A1
公开(公告)日：2024-10-24
申请号：US18760318
申请日：2024-07-01
发明人： Shih Kuang Yang , Ping-Cheng Li , Hung-Ling Shih , Po-Wei Liu , Wen-Tuo Huang , Yu-Ling Hsu , Yong-Shiuan Tsair , Chia-Sheng Lin
CPC分类号： G11C16/08 , G11C11/1657 , H10B12/053 , H10B41/30
摘要： Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.
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公开(公告)号：US11869951B2
公开(公告)日：2024-01-09
申请号：US17462444
申请日：2021-08-31
发明人： Yu-Ling Hsu , Ping-Cheng Li , Hung-Ling Shih , Po-Wei Liu , Wen-Tuo Huang , Yong-Shiuan Tsair , Chia-Sheng Lin , Shih Kuang Yang
IPC分类号： H01L29/423 , H01L23/528 , H01L23/522 , H01L29/40 , H01L21/265 , H01L29/66 , H01L29/788 , H01L21/3213 , H01L21/28
CPC分类号： H01L29/42328 , H01L21/26513 , H01L21/32139 , H01L23/528 , H01L23/5226 , H01L29/401 , H01L29/40114 , H01L29/66825 , H01L29/7881
摘要： Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.
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公开(公告)号：US11798836B2
公开(公告)日：2023-10-24
申请号：US17350930
申请日：2021-06-17
发明人： Tsung-Yu Yang , Po-Wei Liu , Yun-Chi Wu , Yu-Wen Tseng , Chia-Ta Hsieh , Ping-Cheng Li , Tsung-Hua Yang , Yu-Chun Chang
IPC分类号： H01L21/762 , H01L21/74 , H01L23/535
CPC分类号： H01L21/76283 , H01L21/743 , H01L23/535
摘要： A semiconductor isolation structure includes a silicon-on-insulator wafer, a first deep trench isolation structure and a second deep trench isolation structure. The silicon-on-insulator wafer includes a semiconductor substrate, a buried insulation layer disposed on the semiconductor substrate, and a semiconductor layer disposed on the buried insulation layer. The semiconductor layer has a functional region. The first deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional region. The second deep trench isolation structure penetrates semiconductor layer and the buried insulation layer, and surrounds the first deep trench isolation structure.
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公开(公告)号：US20230112168A1
公开(公告)日：2023-04-13
申请号：US18079047
申请日：2022-12-12
发明人： Wen-Tuo Huang , Ping-Cheng Li , Hung-Ling Shih , Po-Wei Liu , Yu-Ling Hsu , Yong-Shiuan Tsair , Chia-Sheng Lin , Shih Kuang Yang
IPC分类号： H01L29/788 , H01L23/532 , H01L29/40 , H01L21/768 , H01L29/423 , H01L21/28 , H01L29/66 , H01L23/522 , H01L29/49 , H01L23/528
摘要： Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.
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公开(公告)号：US09646980B2
公开(公告)日：2017-05-09
申请号：US15061762
申请日：2016-03-04
发明人： Chia-Ta Hsieh , Po-Wei Liu , Yong-Shiuan Tsair , Chieh-Fei Chiu
IPC分类号： H01L27/115 , H01L27/11524 , H01L21/28 , H01L29/66 , H01L27/11521 , H01L27/11529 , H01L27/11548 , H01L29/78
CPC分类号： H01L27/11524 , H01L21/28008 , H01L21/28273 , H01L27/11521 , H01L27/11529 , H01L27/11548 , H01L29/66825 , H01L29/78
摘要： A method includes forming a first pad oxide layer and a second pad oxide layer over a first active region and a second active region, respectively, of a semiconductor substrate, forming a dielectric protection layer overlapping the first pad oxide layer, removing the second pad oxide layer, and forming a floating gate dielectric over the second active region. A floating gate layer is then formed to include a first portion over the dielectric protection layer, and a second portion over the floating gate dielectric. A planarization is performed on the first portion and the second portion of the floating gate layer. A blocking layer, a control gate layer, and a hard mask layer are formed over the second portion of the floating gate layer. The hard mask layer, the control gate layer, and the blocking layer are patterned to form a gate stack for a flash memory cell.
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