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140 条记录 (耗时 0.026 秒)

    INTEGRATED CIRCUIT STRUCTURE
    11.
    发明申请
    INTEGRATED CIRCUIT STRUCTURE 有权

    公开(公告)号：US20230064223A1

    公开(公告)日：2023-03-02

    申请号：US17459697

    申请日：2021-08-27

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Te-Hsin Chiu ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

    IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L21/768

    摘要： An integrated circuit structure is disclosed, including a gate, a first conductive line and a pair of second conductive lines, and a first feed-through via. The gate is disposed on a front side of the integrated circuit structure and extends in a first direction on a first side of a dielectric layer. The first conductive line and a pair of second conductive lines are disposed on a second side, opposite of the first side, of the dielectric layer and on a back side, opposite of the front side, of the integrated circuit structure. The first conductive line is interposed between the pair of second conductive lines in a layout view. The first feed-through via extends through the dielectric layer in a second direction different from the first direction. The first feed-through via couples the gate to the first conductive line.

    TWO-DIMENSIONAL (2D) METAL STRUCTURE
    12.
    发明申请
    TWO-DIMENSIONAL (2D) METAL STRUCTURE 有权

    公开(公告)号：US20230008779A1

    公开(公告)日：2023-01-12

    申请号：US17371321

    申请日：2021-07-09

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Shih-Wei Peng ,  Jiann-Tyng Tzeng ,  Ken-Hsien Hsieh

    IPC分类号： H01L23/528 ,  H01L27/085 ,  H01L27/092 ,  H01L21/768

    摘要： A semiconductor structure includes: a first gate structure and a second gate structure extending in a first direction; a first base level metal interconnect (M0) pattern extending in a second direction perpendicular to the first direction; a second M0 pattern extending in the second direction; a third M0 pattern located between the first and second gate structures and extending in the first direction, two ends of the third M0 pattern connected to the first M0 pattern and the second M0 pattern, respectively; a fourth M0 pattern and a fifth M0 pattern located between the first and second M0 patterns and extending in the second direction. A distance between the fourth M0 pattern and the first M0 pattern in the first direction is equal to a minimum M0 pattern pitch, and a distance between the fourth M0 pattern and the second M0 pattern is equal to the minimum M0 pattern pitch.

    MONOLITHIC THREE DIMENSIONAL INTEGRATED CIRCUIT
    13.
    发明申请
    MONOLITHIC THREE DIMENSIONAL INTEGRATED CIRCUIT 有权

    公开(公告)号：US20220352148A1

    公开(公告)日：2022-11-03

    申请号：US17245757

    申请日：2021-04-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Kam-Tou Sio ,  Jiann-Tyng Tzeng ,  Shih-Wei Peng

    IPC分类号： H01L27/06 ,  H01L23/522 ,  H01L23/528 ,  H01L21/822

    摘要： A monolithic three dimensional integrated circuit is provided. The monolithic three dimensional integrated circuit includes a first cell layer having a first cell having a first active component of the monolithic three dimensional integrated circuit. A second layer having a second cell including a second active component. The second cell layer is formed vertically above the first cell layer. The first cell layer having the first active component and the second cell layer having the second active component are formed on a single die. The first cell has a smaller metal pitch than the second cell. A buried via electrically couples the first active component of the first cell of the first cell layer with the second active component of the second cell of the second cell layer.

    Semiconductor structure and method of forming the same
    14.
    发明授权
    Semiconductor structure and method of forming the same 有权

    公开(公告)号：US11374005B2

    公开(公告)日：2022-06-28

    申请号：US17075578

    申请日：2020-10-20

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： Shih-Wei Peng ,  Te-Hsin Chiu ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

    IPC分类号： H01L21/02 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

    摘要： A semiconductor device includes a first transistor of a first conductivity type and a second transistor of a second conductivity type. The first transistor is arranged in a first layer and includes a gate extending in a first direction and a first active region extending in a second direction perpendicular to the first direction. The second transistor is arranged in a second layer over the first layer and includes the gate and a second active region extending in the second direction. The semiconductor device also includes a first conductive line arranged in a third layer between the first layer and the second layer and extending in the second direction, wherein the first conductive line is configured to electrically connect a first source/drain region of the first active region to a second source/drain region of the second active region.

    Clock circuit and method of operating the same
    19.
    发明授权
    Clock circuit and method of operating the same 有权
    时钟电路及其操作方法

    公开(公告)号：US09442510B2

    公开(公告)日：2016-09-13

    申请号：US14613817

    申请日：2015-02-04

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Jiann-Tyng Tzeng ,  Meng-Hung Shen ,  Yi-Feng Chen ,  Charles Chew-Yuen Young

    IPC分类号： G06F1/04 ,  G06F1/12 ,  H03K19/20

    CPC分类号： H03K19/20 ,  G06F1/04 ,  G06F1/10

    摘要： A clock gating circuit includes a first transistor, a first inverter and a second transistor. A first terminal of the first transistor receives a clock input signal. A second terminal of the first transistor is coupled to a first node. The first transistor adjusts a voltage of the first node to a first voltage based on the clock input signal. The first inverter is coupled to the first node and receives the voltage of the first node, and outputs a clock output signal. A first terminal of the second transistor receives the clock input signal. A second terminal of the second transistor is coupled to the first node and a second node. The second transistor adjusts the voltage of the first node or the second node to the second voltage, based on the clock input signal.

    摘要翻译： 时钟选通电路包括第一晶体管，第一反相器和第二晶体管。 第一晶体管的第一端接收时钟输入信号。 第一晶体管的第二端子耦合到第一节点。 第一晶体管基于时钟输入信号将第一节点的电压调整到第一电压。 第一反相器耦合到第一节点并接收第一节点的电压，并输出时钟输出信号。 第二晶体管的第一端子接收时钟输入信号。 第二晶体管的第二端子耦合到第一节点和第二节点。 第二晶体管基于时钟输入信号将第一节点或第二节点的电压调整到第二电压。