公开(公告)号：US20180374801A1

公开(公告)日：2018-12-27

申请号：US16103259

申请日：2018-08-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Hsien-Wen Liu

IPC: H01L23/00 ,  H01L21/02 ,  H01L23/29 ,  H01L23/31 ,  H01L25/10 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L23/564 ,  H01L21/02118 ,  H01L21/02164 ,  H01L21/0217 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L2224/024 ,  H01L2224/03332 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure.

公开(公告)号：US20180033782A1

公开(公告)日：2018-02-01

申请号：US15223862

申请日：2016-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Hsien-Wen Liu ,  Yi-Jou Lin

IPC: H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L21/288 ,  H01L21/683 ,  H01L21/768

CPC classification number: H01L25/50 ,  H01L21/288 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/76885 ,  H01L25/0657 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572

Abstract: A method includes forming a dielectric layer over a radiation de-bondable coating. The radiation de-bondable coating is over a carrier, and the radiation de-bondable coating includes metal particles therein. Metal posts are formed over the dielectric layer. A device die is attached to the dielectric layer. The device die and the metal posts are encapsulated in an encapsulating material. A plurality of redistribution lines is formed on a first side of the encapsulating material, and is electrically coupled to the device die and the metal posts. The carrier is de-bonded by projecting a radiation source on the radiation de-bondable coating to decompose the radiation de-bondable coating. Electrical connections are formed on a second side of the encapsulating material. The electrical connections are electrically coupled to the metal posts.

公开(公告)号：US20170186736A1

公开(公告)日：2017-06-29

申请号：US15458378

申请日：2017-03-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jui-Pin Hung ,  Cheng-Lin Huang ,  Hsien-Wen Liu ,  Shin-Puu Jeng

IPC: H01L25/10 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L21/561 ,  H01L21/568 ,  H01L23/10 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/83005

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.

公开(公告)号：US20170092597A1

公开(公告)日：2017-03-30

申请号：US15376437

申请日：2016-12-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Hsien-Wen Liu

IPC: H01L23/00 ,  H01L21/02 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L23/564 ,  H01L21/02118 ,  H01L21/02164 ,  H01L21/0217 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L2224/024 ,  H01L2224/03332 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure.

公开(公告)号：US12198996B2

公开(公告)日：2025-01-14

申请号：US17382385

申请日：2021-07-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Hsien-Wen Liu ,  Shih-Ting Hung ,  Yi-Jou Lin ,  Tzu-Jui Fang ,  Po-Yao Chuang

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/528 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

Abstract: An integrated fan-out package includes a first redistribution structure, a die, a plurality of conductive structures, an encapsulant, and a second redistribution structure. The die is bonded to the first redistribution structure through flip-chip bonding. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is disposed on the encapsulant and is electrically connected to the first redistribution structure through the conductive structures. The second redistribution structure includes at least one conductive pattern layer that is in physical contact with the encapsulant. Top surfaces of the conductive structures contacting the second redistribution structure are coplanar with a top surface of the encapsulant.

公开(公告)号：US11756928B2

公开(公告)日：2023-09-12

申请号：US17726545

申请日：2022-04-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Han-Hsiang Huang ,  Hsien-Wen Liu ,  Shin-Puu Jeng ,  Hsiao-Wen Lee

IPC: H01L25/065 ,  H01L25/16 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31

CPC classification number: H01L25/0652 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5383 ,  H01L25/16 ,  H01L25/50 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2225/06517 ,  H01L2225/06548

Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

公开(公告)号：US11342306B2

公开(公告)日：2022-05-24

申请号：US17006863

申请日：2020-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Han-Hsiang Huang ,  Hsien-Wen Liu ,  Shin-Puu Jeng ,  Hsiao-Wen Lee

IPC: H01L25/065 ,  H01L25/16 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31

Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

公开(公告)号：US20210358824A1

公开(公告)日：2021-11-18

申请号：US17382385

申请日：2021-07-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Hsien-Wen Liu ,  Shih-Ting Hung ,  Yi-Jou Lin ,  Tzu-Jui Fang ,  Po-Yao Chuang

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/528 ,  H01L25/00 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

Abstract: An integrated fan-out package includes a first redistribution structure, a die, a plurality of conductive structures, an encapsulant, and a second redistribution structure. The die is bonded to the first redistribution structure through flip-chip bonding. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is disposed on the encapsulant and is electrically connected to the first redistribution structure through the conductive structures. The second redistribution structure includes at least one conductive pattern layer that is in physical contact with the encapsulant. Top surfaces of the conductive structures contacting the second redistribution structure are coplanar with a top surface of the encapsulant.

公开(公告)号：US10748882B2

公开(公告)日：2020-08-18

申请号：US16126835

申请日：2018-09-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jui-Pin Hung ,  Cheng-Lin Huang ,  Hsien-Wen Liu ,  Shin-Puu Jeng

IPC: H01L25/10 ,  H01L21/56 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L23/10

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.

公开(公告)号：US20200098705A1

公开(公告)日：2020-03-26

申请号：US16696771

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Hsien-Wen Liu

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/538 ,  H01L23/31 ,  H01L23/29 ,  H01L21/02

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure.