公开(公告)号：US10290590B2

公开(公告)日：2019-05-14

申请号：US15485530

申请日：2017-04-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shin-Puu Jeng ,  Tzu-Jui Fang ,  Hsi-Kuei Cheng ,  Chih-Kang Han ,  Yi-Jen Lai ,  Hsien-Wen Liu ,  Yi-Jou Lin

IPC: H01L23/58 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/373 ,  H01L23/538 ,  H01L25/10 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498

Abstract: A semiconductor device includes: a first dielectric layer having a first surface; a molding compound disposed on the first surface of the first dielectric layer; a second dielectric layer having a first surface disposed on the molding compound; a via disposed in the molding compound; and a first conductive bump disposed on the via and surrounded by the second dielectric layer; wherein the first dielectric layer and the second dielectric layer are composed of the same material. The filling material has a thickness between the second dielectric layer and the semiconductor die, and the diameter of the hole is inversely proportional to the thickness of the filling material.

公开(公告)号：US20240387308A1

公开(公告)日：2024-11-21

申请号：US18786596

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Hsien-Wen Liu ,  Shih-Ting Hung ,  Yi-Jou Lin ,  Tzu-Jui Fang ,  Po-Yao Chuang

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/528 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

Abstract: A manufacturing method of a package-on-package structure includes forming a first package structure and staking a second package structure over the first package structure. The first package structure is formed by at least the following steps. A first redistribution structure is provided. Conductive structures are formed on the first redistribution structure. A die is placed between the conductive structures. The die and the conductive structures are encapsulated by an encapsulant. The encapsulant is planarized such that an entirety of a top surface of the encapsulant is coplanar with an entirety of top surfaces of the conductive structures. A second redistribution structure is formed on the encapsulant. The second redistribution structure includes a conductive pattern layer that is in physical contact with the top surfaces of the encapsulant and the conductive structures. An entire bottom surface of the conductive pattern layer is located at a same level height.

公开(公告)号：US12198996B2

公开(公告)日：2025-01-14

申请号：US17382385

申请日：2021-07-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Hsien-Wen Liu ,  Shih-Ting Hung ,  Yi-Jou Lin ,  Tzu-Jui Fang ,  Po-Yao Chuang

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/528 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

Abstract: An integrated fan-out package includes a first redistribution structure, a die, a plurality of conductive structures, an encapsulant, and a second redistribution structure. The die is bonded to the first redistribution structure through flip-chip bonding. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is disposed on the encapsulant and is electrically connected to the first redistribution structure through the conductive structures. The second redistribution structure includes at least one conductive pattern layer that is in physical contact with the encapsulant. Top surfaces of the conductive structures contacting the second redistribution structure are coplanar with a top surface of the encapsulant.

公开(公告)号：US20210358824A1

公开(公告)日：2021-11-18

申请号：US17382385

申请日：2021-07-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Hsien-Wen Liu ,  Shih-Ting Hung ,  Yi-Jou Lin ,  Tzu-Jui Fang ,  Po-Yao Chuang

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/528 ,  H01L25/00 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

Abstract: An integrated fan-out package includes a first redistribution structure, a die, a plurality of conductive structures, an encapsulant, and a second redistribution structure. The die is bonded to the first redistribution structure through flip-chip bonding. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is disposed on the encapsulant and is electrically connected to the first redistribution structure through the conductive structures. The second redistribution structure includes at least one conductive pattern layer that is in physical contact with the encapsulant. Top surfaces of the conductive structures contacting the second redistribution structure are coplanar with a top surface of the encapsulant.