公开(公告)号：US20210233921A1

公开(公告)日：2021-07-29

申请号：US17231204

申请日：2021-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Harry-Hak-Lay Chuang

IPC: H01L27/11521 ,  H01L27/11568 ,  H01L27/11563 ,  H01L21/28 ,  H01L27/105 ,  H01L27/11546 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/321

Abstract: An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.

公开(公告)号：US11063208B2

公开(公告)日：2021-07-13

申请号：US16672110

申请日：2019-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Jun-Yao Chen ,  Hung Cho Wang

IPC: G11C11/00 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: An integrated circuit die includes a magnetic tunnel junction as a storage element of a MRAM cell. The integrated circuit die includes a top electrode positioned on the magnetic tunnel junction. The integrated circuit die includes a first sidewall spacer laterally surrounding the top electrode. The first sidewall spacer acts as a mask for patterning the magnetic tunnel junction. The integrated circuit die includes a second sidewalls spacer positioned on a lateral surface of the magnetic tunnel junction.

公开(公告)号：US10937957B2

公开(公告)日：2021-03-02

申请号：US16587430

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Tien-Wei Chiang ,  Wen-Chun You

IPC: H01L29/82 ,  H01L43/12 ,  H01L27/22 ,  H01L43/08

Abstract: Some embodiments relate to a magnetoresistive random-access memory (MRAM) cell. The cell includes a bottom electrode having a central bottom electrode portion surrounded by a peripheral bottom electrode portion. Step regions of the conductive bottom electrode couple the central and peripheral bottom electrode portions to one another such that an upper surface of the central portion is recessed relative to an upper surface of the peripheral portion. A magnetic tunneling junction (MTJ) has MTJ outer sidewalls which are disposed over the bottom central electrode portion and which are arranged between the step regions. A top electrode is disposed over an upper surface of the MTJ. Other devices and methods are also disclosed.

公开(公告)号：US20210028350A1

公开(公告)日：2021-01-28

申请号：US17009905

申请日：2020-09-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Che Ku ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Tsun Chung Tu ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC: H01L43/02 ,  H01F10/32 ,  H01L27/22 ,  H01L43/12 ,  H01L23/528 ,  H01L21/768 ,  H01F41/34 ,  H01L23/522

Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming an ILD layer over a memory device over a substrate. A hard mask structure is formed over the ILD layer and a patterning structure is formed over the hard mask structure. The hard mask structure has sidewalls defining a first opening directly over the memory device and centered along a first line perpendicular to an upper surface of the substrate. The patterning structure has sidewalls defining a second opening directly over the memory device and centered along a second line parallel to the first line. The second line is laterally offset from the first line by a non-zero distance. The ILD layer is etched below an overlap of the first and second openings to define a top electrode via hole. The top electrode via hole is with a conductive material.

公开(公告)号：US20200350366A1

公开(公告)日：2020-11-05

申请号：US16930499

申请日：2020-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chang Chen ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Sheng-Huang Huang

IPC: H01L27/22 ,  H01L43/02 ,  H01F10/32 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L43/12 ,  H01F41/32 ,  H01L23/532

Abstract: Some embodiments relate to an integrated chip. The integrated chip includes a first memory cell overlying a substrate and a second memory cell overlying the substrate. A dielectric structure overlies the substrate. A trench extends into the dielectric structure and is spaced laterally between the first memory cell and the second memory cell. A dielectric layer is disposed within the trench.

公开(公告)号：US10797230B2

公开(公告)日：2020-10-06

申请号：US16580419

申请日：2019-09-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC: G11C11/00 ,  H01L43/02 ,  G11C11/16 ,  H01L43/12

Abstract: Some embodiments relate to a method for manufacturing a magnetoresistive random-access memory (MRAM) cell. The method includes forming a spacer layer surrounding at least a magnetic tunnel junction (MTJ) layer and a top electrode of the MRAM cell; etching the spacer layer to expose a top surface of the top electrode and a top surface of a spacer formed by the spacer layer; forming an upper etch stop layer over the top electrode top surface and the spacer top surface; and forming an upper metal layer in contact with the top electrode top surface of the MRAM cell. A width of the upper etch stop layer is greater than a width of a bottom surface of the upper metal layer.

公开(公告)号：US10276588B2

公开(公告)日：2019-04-30

申请号：US15582889

申请日：2017-05-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Yi Hsien Lu

IPC: H01L21/336 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L21/8234 ,  H01L27/092 ,  H01L27/088

Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-κ metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.

公开(公告)号：US10050047B2

公开(公告)日：2018-08-14

申请号：US15489287

申请日：2017-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chin-Yi Huang ,  Ya-Chen Kao

IPC: H01L27/11507 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/66 ,  H01L27/11521 ,  H01L21/28 ,  H01L21/321

Abstract: The present disclosure relates a method for manufacturing an integrated circuit. In some embodiments, a semiconductor substrate is provided and made up of a memory array region and a boundary region surrounding the memory array region. A hard mask layer is formed over the memory array region and the boundary region. The hard mask layer is patterned to form a boundary hard mask having one or more slots to expose some portions of the boundary region while the remaining regions of the boundary region are covered by the boundary hard mask. A floating gate layer is formed within the memory array region and extending over the hard mask layer. Then, a planarization is performed to reduce a height of the floating gate layer and form a plurality of floating gates.

公开(公告)号：US10038137B2

公开(公告)日：2018-07-31

申请号：US15281428

申请日：2016-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Sheng-Haung Huang ,  Hung-Cho Wang ,  Kuei-Hung Shen ,  Shy-Jay Lin

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02

CPC classification number: H01L43/08 ,  H01L27/222 ,  H01L43/02 ,  H01L43/12

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a magnetoresistive random access memory (MRAM) device in an insulating layer. The MRAM device includes a first electrode, a magnetic tunnel junction (MTJ) over the first electrode, a second electrode over the MTJ, and an insulating spacer surrounding sidewalls of the first electrode, the MTJ, and the second electrode. Top surfaces of the insulating spacer and the second electrode are exposed from the insulating layer. The semiconductor device structure also includes a conductive pad over the insulating layer and electrically connected to the second electrode. The MTJ is entirely covered by the conductive pad.

公开(公告)号：US09985075B2

公开(公告)日：2018-05-29

申请号：US15345928

申请日：2016-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wen-Chun You

IPC: H01L27/00 ,  H01L27/24 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L43/02 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

Abstract: The present disclosure relates an integrated circuit (IC). A plurality of metal layers is disposed within an inter-layer dielectric (ILD) material over the substrate. A memory cell is disposed over a first metal layer at a memory region and comprising a bottom electrode directly above a first metal line within the first metal layer and a top electrode separated from the bottom electrode by a resistance switching element. A dummy structure comprises a dummy bottom electrode arranged directly above a second metal line within the first metal layer at a logic region adjacent to the memory region.