公开(公告)号：US11264561B2

公开(公告)日：2022-03-01

申请号：US16809998

申请日：2020-03-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Che Ku ,  Jun-Yao Chen ,  Sheng-Huang Huang ,  Jiun-Yu Tsai ,  Harry-Hak-Lay Chuang ,  Hung-Cho Wang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A method of forming a magnetic random access memory (MRAM) device includes forming a bottom electrode layer over a substrate including an inter-metal dielectric (IMD) layer having a metal line therein; forming a barrier layer over the bottom electrode layer; forming a magnetic tunnel junction (MTJ) layer stack over the bottom electrode layer; forming a dielectric layer over the MTJ layer stack; forming an opening in the dielectric layer to expose the barrier layer; filling the opening in the dielectric layer with a top electrode; after filling the opening in the dielectric layer with the top electrode, etching the dielectric layer to expose the barrier layer; and patterning the MTJ layer stack to form an MTJ stack that exposes the bottom electrode layer.

公开(公告)号：US12223989B2

公开(公告)日：2025-02-11

申请号：US18151994

申请日：2023-01-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry-Hak-Lay Chuang ,  Sheng-Huang Huang ,  Hung-Cho Wang ,  Sheng-Chang Chen

IPC: G11C11/16 ,  G11C5/02 ,  G11C5/06 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a first memory cell and a second memory cell over a substrate, wherein each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element; depositing a first dielectric layer over the first and second memory cells, such that the first dielectric layer has a void between the first and second memory cells; depositing a second dielectric layer over the first dielectric layer; and forming a first conductive feature and a second conductive feature in the first and second dielectric layers and respectively connected with the top electrode of the first memory cell and the top electrode of the second memory cell.

公开(公告)号：US11502126B2

公开(公告)日：2022-11-15

申请号：US17097485

申请日：2020-11-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry-Hak-Lay Chuang ,  Sheng-Wen Fu ,  Jun-Yao Chen ,  Sheng-Huang Huang ,  Hung-Cho Wang

IPC: H01L27/22 ,  H01L21/768 ,  H01L43/12

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing an etch stop layer over an interconnect layer having a conductive feature; depositing a protective layer over the etch stop layer; depositing a first dielectric layer over the protective layer; etching a via opening in the first dielectric layer, wherein the protective layer has a higher etch resistance to etching the via opening than that of the first dielectric layer; etching a portion of the protective layer exposed by the via opening; etching a portion of the etch stop layer exposed by the via opening, such that the via opening exposes the conductive feature; forming a bottom electrode via in the via opening; and forming a memory stack over the bottom electrode via.

公开(公告)号：US10038137B2

公开(公告)日：2018-07-31

申请号：US15281428

申请日：2016-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Sheng-Haung Huang ,  Hung-Cho Wang ,  Kuei-Hung Shen ,  Shy-Jay Lin

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02

CPC classification number: H01L43/08 ,  H01L27/222 ,  H01L43/02 ,  H01L43/12

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a magnetoresistive random access memory (MRAM) device in an insulating layer. The MRAM device includes a first electrode, a magnetic tunnel junction (MTJ) over the first electrode, a second electrode over the MTJ, and an insulating spacer surrounding sidewalls of the first electrode, the MTJ, and the second electrode. Top surfaces of the insulating spacer and the second electrode are exposed from the insulating layer. The semiconductor device structure also includes a conductive pad over the insulating layer and electrically connected to the second electrode. The MTJ is entirely covered by the conductive pad.

公开(公告)号：US11569443B2

公开(公告)日：2023-01-31

申请号：US16935139

申请日：2020-07-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry-Hak-Lay Chuang ,  Sheng-Huang Huang ,  Hung-Cho Wang

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A method for fabricating the semiconductor device is provided. The method includes depositing a first dielectric layer; forming a first memory cell over the first dielectric layer; depositing a second dielectric layer over the first memory cell; and forming a second memory cell over the second dielectric layer. Forming the first memory cell includes depositing a first resistance switching layer over the first dielectric layer and performing a first physical etching process to pattern the first resistance switching layer into a first resistance switching element. Forming the second memory cell includes depositing a second resistance switching layer over the second dielectric layer and performing a chemical etching process to pattern the second resistance switching layer into a second resistance switching element.

公开(公告)号：US11283009B2

公开(公告)日：2022-03-22

申请号：US16702137

申请日：2019-12-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry-Hak-Lay Chuang ,  Chun-Heng Liao ,  Jun-Yao Chen ,  Hung-Cho Wang

IPC: H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  H01L27/22

Abstract: A method for manufacturing a memory device is provided. The method includes forming a bottom electrode layer, a resistance switching element layer over the bottom electrode layer, and a top electrode layer over the resistance switching element layer; patterning the top electrode layer into a top electrode; forming a protection spacer on a sidewall of the top electrode; patterning the resistance switching element layer into a resistance switching element after forming the protection spacer; and patterning the bottom electrode layer into a bottom electrode after patterning the resistance switching element layer.

公开(公告)号：US11189791B2

公开(公告)日：2021-11-30

申请号：US16789736

申请日：2020-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Che Ku ,  Jiun-Yu Tsai ,  Hung-Cho Wang

IPC: H01L45/00 ,  H01L27/24 ,  H01L21/768

Abstract: A method for fabricating an integrated circuit is provided. The method includes forming a memory cell over a substrate, wherein the memory cell comprising a top electrode, a bottom electrode, and a resistance switching element between the bottom electrode and the top electrode; forming a dielectric layer over the memory cell and the substrate; etching a via opening in the dielectric layer to expose the top electrode of the memory cell; forming a spacer in the via opening; performing a liner removal process to the dielectric layer after forming the spacer; and forming a conductive feature connected to the top electrode in the via opening.

公开(公告)号：US11551736B2

公开(公告)日：2023-01-10

申请号：US16943990

申请日：2020-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry-Hak-Lay Chuang ,  Sheng-Huang Huang ,  Hung-Cho Wang ,  Sheng-Chang Chen

IPC: G11C11/16 ,  H01L27/22 ,  G11C5/02 ,  H01L43/02 ,  G11C5/06 ,  H01L43/12

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a first memory cell and a second memory cell over a substrate, wherein each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element; depositing a first dielectric layer over the first and second memory cells, such that the first dielectric layer has a void between the first and second memory cells; depositing a second dielectric layer over the first dielectric layer; and forming a first conductive feature and a second conductive feature in the first and second dielectric layers and respectively connected with the top electrode of the first memory cell and the top electrode of the second memory cell.

公开(公告)号：US11217627B2

公开(公告)日：2022-01-04

申请号：US16886480

申请日：2020-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry-Hak-Lay Chuang ,  Jiun-Yu Tsai ,  Sheng-Huang Huang ,  Ming-Che Ku ,  Hung-Cho Wang

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  H01L23/522 ,  H01L23/528 ,  H01L43/10

Abstract: A method of forming a MRAM device includes forming an interconnect structure spanning a memory region and a peripheral region; forming a MTJ stack over the interconnect structure within the memory region; depositing a dielectric layer over the MTJ stack and spanning the memory region and the peripheral region; removing a first portion of the dielectric layer from the peripheral region, while leaving a second portion of the dielectric layer within the memory region; after removing the first portion of the dielectric layer from the peripheral region, forming a first IMD layer spanning the memory region and the peripheral region; forming a dual damascene structure through the first IMD layer to a metallization pattern of the interconnect structure within the peripheral region; and after forming the dual damascene structure within the peripheral region, forming a top electrode via in contact with a top electrode of the MTJ stack.

公开(公告)号：US20210057639A1

公开(公告)日：2021-02-25

申请号：US16809998

申请日：2020-03-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Che KU ,  Jun-Yao CHEN ,  Sheng-Huang HUANG ,  Jiun-Yu TSAI ,  Harry-Hak-Lay Chuang ,  Hung-Cho Wang

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: A method of forming a magnetic random access memory (MRAM) device includes forming a bottom electrode layer over a substrate including an inter-metal dielectric (IMD) layer having a metal line therein; forming a barrier layer over the bottom electrode layer; forming a magnetic tunnel junction (MTJ) layer stack over the bottom electrode layer; forming a dielectric layer over the MTJ layer stack; forming an opening in the dielectric layer to expose the barrier layer; filling the opening in the dielectric layer with a top electrode; after filling the opening in the dielectric layer with the top electrode, etching the dielectric layer to expose the barrier layer; and patterning the MTJ layer stack to form an MTJ stack that exposes the bottom electrode layer.