公开(公告)号：US20200152763A1

公开(公告)日：2020-05-14

申请号：US16740881

申请日：2020-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wen Cheng ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Hong-Mao Lee ,  Ming-Hsing Tsai ,  Sheng-Hsuan Lin ,  Wei-Jung Lin ,  Yan-Ming Tsai ,  Yu-Shiuan Wang ,  Hung-Hsu Chen ,  Wei-Yip Loh ,  Ya-Yi Cheng

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L29/78 ,  H01L21/02 ,  H01L21/326 ,  H01L29/45

Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.

公开(公告)号：US10325994B2

公开(公告)日：2019-06-18

申请号：US15959900

申请日：2018-04-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Tang Peng ,  Tai-Chun Huang ,  Teng-Chun Tsai ,  Cheng-Tung Lin ,  De-Fang Chen ,  Li-Ting Wang ,  Chien-Hsun Wang ,  Huan-Just Lin ,  Yung-Cheng Lu ,  Tze-Liang Lee

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L21/02 ,  H01L23/00 ,  H01L29/78 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/775 ,  H01L29/06 ,  H01L23/29 ,  H01L23/31 ,  H01L27/088

Abstract: According to an exemplary embodiment, a method of forming a vertical structure with at least two barrier layers is provided. The method includes the following operations: providing a substrate; providing a vertical structure over the substrate; providing a first barrier layer over a source, a channel, and a drain of the vertical structure; and providing a second barrier layer over a gate and the drain of the vertical structure.

公开(公告)号：US09941394B2

公开(公告)日：2018-04-10

申请号：US14460214

申请日：2014-08-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Teng-Chun Tsai ,  Cheng-Tung Lin ,  Li-Ting Wang ,  Chih-Tang Peng ,  De-Fang Chen ,  Hung-Ta Lin ,  Chien-Hsun Wang

IPC: H01L29/06 ,  H01L29/739 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L21/265 ,  H01L29/51 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775 ,  H01L29/16

CPC classification number: H01L29/7391 ,  B82Y10/00 ,  H01L21/265 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823487 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/66356 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/66977 ,  H01L29/775 ,  H01L29/7827

Abstract: The tunnel field-effect transistor includes a drain layer, a source layer, a channel layer, a metal gate layer, and a high-k dielectric layer. The drain and source layers are of opposite conductive types. The channel layer is disposed between the drain layer and the source layer. At least one of the drain layer, the channel layer, and the source layer has a substantially constant doping concentration. The metal gate layer is disposed around the channel layer. The high-k dielectric layer is disposed between the metal gate layer and the channel layer.