公开(公告)号：US11903188B2

公开(公告)日：2024-02-13

申请号：US17673126

申请日：2022-02-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Perng-Fei Yuh ,  Yih Wang ,  Meng-Sheng Chang ,  Jui-Che Tsai ,  Ku-Feng Lin ,  Yu-Wei Lin ,  Keh-Jeng Chang ,  Chansyun David Yang ,  Shao-Ting Wu ,  Shao-Yu Chou ,  Philex Ming-Yan Fan ,  Yoshitaka Yamauchi ,  Tzu-Hsien Yang

IPC: G11C17/16 ,  H10B20/20 ,  G11C17/18

CPC classification number: H10B20/20 ,  G11C17/16 ,  G11C17/18

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

公开(公告)号：US10128195B2

公开(公告)日：2018-11-13

申请号：US15226246

申请日：2016-08-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Wei Lin ,  Guan-Yu Chen ,  Yu-Min Liang ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H05K1/18 ,  H01L23/00 ,  H01L23/498 ,  H01L23/13

Abstract: A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1.

公开(公告)号：US09812405B2

公开(公告)日：2017-11-07

申请号：US15223371

申请日：2016-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Guan-Yu Chen ,  Yu-Wei Lin ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/66 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L22/12 ,  H01L22/20 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17106 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/381 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The present disclosure provides a method for manufacturing a semiconductor package. The method includes (1) determining a die warpage value under a predetermined temperature range; (2) determining a difference between a density of a top metal and a density of a bottom metal of a substrate according to the die warpage value; and (3) joining the die and the substrate under the predetermined temperature range. The top metal includes all metal layers overlying a middle layer, and the bottom metal includes all metal layers underlying the middle layer. The middle layer includes a core or a metal layer.

公开(公告)号：US20160365322A1

公开(公告)日：2016-12-15

申请号：US15226246

申请日：2016-08-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Wei Lin ,  Guan-Yu Chen ,  Yu-Min Liang ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16013 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/3841 ,  H05K1/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1.

公开(公告)号：US20150130050A1

公开(公告)日：2015-05-14

申请号：US14080106

申请日：2013-11-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Wei Lin ,  Guan-Yu Chen ,  Yu-Min Liang ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16013 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/3841 ,  H05K1/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1.

Abstract translation: 封装包括封装基板，其包括从由中心层和中间金属层组成的组中选择的中间层，覆盖中间层的顶部金属层和位于中间层下面的底部金属层。 覆盖中间层的所有金属层具有等于中间层上所有金属层的所有密度的总和的第一总金属密度。 中间层下面的所有金属层具有第二总金属密度，其等于中间层下的所有金属层的所有密度的总和。 第一总金属密度和第二总金属密度之差的绝对值低于约0.1。

公开(公告)号：US20250054900A1

公开(公告)日：2025-02-13

申请号：US18366620

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Yen Lan ,  Chih-Chien Pan ,  Pu Wang ,  Li-Hui Cheng ,  Ying-Ching Shih ,  Yu-Wei Lin

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16

Abstract: A package structure includes a circuit substrate, a package unit, a thermal interface material and a cover. The package unit is disposed on and electrically connected with the circuit substrate. The package unit includes a first surface facing the circuit substrate and a second surface opposite to the first surface. A underfill is disposed between the package unit and the circuit substrate, surrounding the package unit and partially covering sidewalls of the package unit. The cover is disposed over the package unit and over the circuit substrate. An adhesive is disposed on the circuit substrate and between the cover and the circuit substrate. The thermal interface material includes a metal-type thermal interface material and is disposed between the cover and the package unit. The thermal interface material physically contacts the second surface and the sidewalls of the package unit and physically contacts the underfill.

公开(公告)号：US20230067664A1

公开(公告)日：2023-03-02

申请号：US17865399

申请日：2022-07-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chao-Wei Li ,  Tzu-Ting Chou ,  Chun-Yen Lan ,  Yu-Wei Lin ,  Sheng-Hsiang Chiu ,  Chih-Wei Lin ,  Ching-Hua Hsieh

IPC: H01L23/31 ,  H01L25/16 ,  H01L25/065 ,  H01L21/56 ,  H01L23/367

Abstract: A package structure includes a circuit substrate, a package element and a molding layer. The package element is disposed on the circuit substrate and is electrically connected with the circuit substrate. The molding layer is disposed over the circuit substrate and covers at least a top surface of the circuit substrate. The molding layer includes a first portion wrapping around sidewalls of the package element and having a first thickness, and a second portion surrounding the first portion and connected with the first portion. The first thickness of the first portion is larger than a second thickness of the second portion. A top surface of the first portion of the molding layer is higher than a top surface of the package element.

公开(公告)号：US11587887B2

公开(公告)日：2023-02-21

申请号：US17148572

申请日：2021-01-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Wei Lin ,  Chun-Yen Lan ,  Tzu-Ting Chou ,  Tzu-Shiun Sheu ,  Chih-Wei Lin ,  Shih-Peng Tai ,  Wei-Cheng Wu ,  Ching-Hua Hsieh

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/367 ,  H01L23/538 ,  H01L21/48

Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a package frame. The semiconductor package is disposed on the circuit substrate. The package frame is disposed over the circuit substrate. The package frame encircles the semiconductor package. The semiconductor package has a first surface facing the circuit substrate and a second surface opposite to the first surface. The package frame leaves exposed at least a portion of the second surface of the semiconductor package. The package frame forms a cavity, which cavity encircles the semiconductor package.

公开(公告)号：US11043462B2

公开(公告)日：2021-06-22

申请号：US16436626

申请日：2019-06-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Wei Lin ,  Sheng-Yu Wu ,  Yu-Jen Tseng ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/00 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L23/498

Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

公开(公告)号：US20190295971A1

公开(公告)日：2019-09-26

申请号：US16436626

申请日：2019-06-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Wei Lin ,  Sheng-Yu Wu ,  Yu-Jen Tseng ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/768

Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.