公开(公告)号：US11646079B2

公开(公告)日：2023-05-09

申请号：US17337781

申请日：2021-06-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Der Chih ,  Maybe Chen ,  Yun-Sheng Chen ,  Wen Zhang Lin ,  Jonathan Tsung-Yung Chang ,  Chrong Jung Lin ,  Ya-Chin King ,  Hsin-Yuan Yu

IPC: G11C11/00 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/004 ,  G11C13/0069 ,  H01L27/2436 ,  H01L45/1206 ,  G11C2013/0045 ,  G11C2013/0078

Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.

公开(公告)号：US12211949B2

公开(公告)日：2025-01-28

申请号：US18486114

申请日：2023-10-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  NATIONAL TSING HUA UNIVERSITY

Inventor： Ya-Chin King ,  Chrong Jung Lin ,  Burn Jeng Lin ,  Shi-Jiun Wang

IPC: H01L31/119 ,  H01L31/0224

Abstract: A device includes an active region, an isolation structure, a gate structure, an interlayer dielectric (ILD) layer, a reading contact, and a sensing contact. The isolation structure laterally surrounds the active region. The gate structure is across the active region. The ILD layer laterally surrounds the gate structure. The reading contact is in contact with the isolation structure and is separated from the gate structure by a first portion of the ILD layer. The sensing contact is in contact with the isolation structure and is separated from the gate structure by a second portion of the ILD layer.

公开(公告)号：US12041860B2

公开(公告)日：2024-07-16

申请号：US17581153

申请日：2022-01-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Der Chih ,  Wen-Zhang Lin ,  Yun-Sheng Chen ,  Jonathan Tsung-Yung Chang ,  Chrong-Jung Lin ,  Ya-Chin King ,  Cheng-Jun Lin ,  Wang-Yi Lee

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/021 ,  H10B63/80 ,  H10N70/063 ,  H10N70/066 ,  H10N70/068 ,  H10N70/841

Abstract: A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.

公开(公告)号：US11943936B2

公开(公告)日：2024-03-26

申请号：US17400615

申请日：2021-08-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yu-Der Chih ,  May-Be Chen ,  Yun-Sheng Chen ,  Jonathan Tsung-Yung Chang ,  Wen Zhang Lin ,  Chrong Jung Lin ,  Ya-Chin King ,  Chieh Lee ,  Wang-Yi Lee

IPC: H10B63/00 ,  H01L29/40 ,  H01L29/78

CPC classification number: H10B63/30 ,  H01L29/401 ,  H01L29/785

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first transistor, a first resistive random access memory (RRAM) resistor, and a second RRAM resistor. The first resistor includes a first resistive material layer, a first electrode shared by the second resistor, and a second electrode. The second resistor includes the first electrode, a second resistive material layer, and a third electrode. The first electrode is electrically coupled to the first transistor.

公开(公告)号：US11824133B2

公开(公告)日：2023-11-21

申请号：US17670309

申请日：2022-02-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  NATIONAL TSING HUA UNIVERSITY

Inventor： Ya-Chin King ,  Chrong Jung Lin ,  Burn Jeng Lin ,  Shi-Jiun Wang

IPC: H01L31/119 ,  H01L31/0224

CPC classification number: H01L31/119 ,  H01L31/022408

Abstract: A device includes a semiconductor fin, an isolation structure, a gate structure, source/drain structures, a sensing contact, a sensing pad structure, and a reading contact. The semiconductor fin includes a channel region and source/drain regions on opposite sides of the channel region. The isolation structure laterally surrounds the semiconductor fin. The gate structure is over the channel region of the semiconductor fin. The source/drain structures are respectively over the source/drain regions of the semiconductor fin. The sensing contact is directly on the isolation structure and adjacent to the gate structure. The sensing pad structure is connected to the sensing contact. The reading contact is directly on the isolation structure and adjacent to the gate structure.

公开(公告)号：US11695082B2

公开(公告)日：2023-07-04

申请号：US17349921

申请日：2021-06-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jiun Shiung Wu ,  Ya-Chin King ,  Chrong-Jung Lin

IPC: H01L29/788 ,  H10B41/10 ,  H10B41/35 ,  H10B41/40 ,  H01L29/78

CPC classification number: H01L29/7883 ,  H01L29/7881 ,  H10B41/10 ,  H10B41/35 ,  H10B41/40 ,  H01L29/785

Abstract: A non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a first fin and a second fin, wherein the second fin is located at a first side of the first fin and a conductive type of the second fin is different from that of the first fin. The insulators are located over the substrate, wherein the first fin and the second fin are respectively located between the insulators. The floating gate is located over the first fin, the insulators and the second fin. The control gate includes the second fin.