公开(公告)号：US11681853B2

公开(公告)日：2023-06-20

申请号：US17692767

申请日：2022-03-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Sheng-Hsiung Chen ,  Wen-Hao Chen ,  Hung-Chih Ou ,  Chun-Yao Ku ,  Shao-Huan Wang

IPC: G06F30/30 ,  G06F30/398 ,  G06F30/3315 ,  G06F30/337 ,  G06F30/396 ,  G06F115/06 ,  G06F119/06 ,  G06F119/12 ,  G06F30/392

CPC classification number: G06F30/398 ,  G06F30/337 ,  G06F30/3315 ,  G06F30/396 ,  G06F30/392 ,  G06F2115/06 ,  G06F2119/06 ,  G06F2119/12

Abstract: A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first inverter is configured to receive a first clock signal on a first clock pin, and is configured to generate a second clock signal inverted from the first clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.

公开(公告)号：US11574107B2

公开(公告)日：2023-02-07

申请号：US17339162

申请日：2021-06-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Pin-Dai Sue ,  Po-Hsiang Huang ,  Fong-Yuan Chang ,  Chi-Yu Lu ,  Sheng-Hsiung Chen ,  Chin-Chou Liu ,  Lee-Chung Lu ,  Yen-Hung Lin ,  Li-Chun Tien ,  Yi-Kan Cheng

IPC: G06F30/00 ,  G06F30/392 ,  G06F30/394 ,  G06F111/20

Abstract: A method of manufacturing a semiconductor device includes forming a transistor layer with an M*1st layer that overlays the transistor layer with one or more first conductors that extend in a first direction. Forming an M*2nd layer that overlays the M*1st layer with one or more second conductors which extend in a second direction. Forming a first pin in the M*2nd layer representing an output pin of a cell region. Forming a long axis of the first pin substantially along a selected one of the one or more second conductors. Forming a majority of the total number of pins in the M*1st layer, the forming including: forming second, third, fourth and fifth pins in the M*1st layer representing corresponding input pins of the circuit; and forming long axes of the second to fifth pins substantially along corresponding ones of the one or more first conductors.

公开(公告)号：US20230023165A1

公开(公告)日：2023-01-26

申请号：US17937654

申请日：2022-10-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Hsiung Chen ,  Huang-Yu Chen ,  Chung-Hsing Wang ,  Jerry Chang Jui Kao

IPC: G06F30/3947 ,  G06F30/39

Abstract: The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.

公开(公告)号：US11138362B2

公开(公告)日：2021-10-05

申请号：US17018759

申请日：2020-09-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Po-Hsiang Huang ,  Sheng-Hsiung Chen ,  Fong-Yuan Chang

IPC: G06F30/398 ,  H01L27/02 ,  G03F1/36 ,  H01L27/118 ,  G06F30/392 ,  G06F30/394 ,  G06F111/04 ,  G06F119/18

Abstract: A method of updating a boundary space configuration of an IC layout cell includes identifying a pin in the IC layout cell as a boundary pin, determining that a boundary spacing of the boundary pin is capable of being increased, and based on the determination that the boundary spacing of the boundary pin is capable of being increased, modifying the IC layout cell by increasing the boundary spacing of the boundary pin. At least one of the identifying, determining, or modifying is executed by a processor of a computer.

公开(公告)号：US11080453B2

公开(公告)日：2021-08-03

申请号：US16599552

申请日：2019-10-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Po-Hsiang Huang ,  Sheng-Hsiung Chen ,  Chih-Hsin Ko ,  Fong-Yuan Chang ,  Clement Hsingjen Wann ,  Li-Chun Tien ,  Chia-Ming Hsu

IPC: G11C11/4076 ,  G11C11/4094 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G06F30/392 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  G06F30/367 ,  G06F30/398 ,  G06F30/3312 ,  G06F111/20

Abstract: A method of operating an IC manufacturing system includes determining whether an n-type active region of a cell or a p-type active region of the cell is a first active region based on a timing critical path of the cell, positioning the first active region along a cell height direction in an IC layout diagram of a cell, the first active region having a first total number of fins extending in a direction perpendicular to the cell height direction. The method also includes positioning a second active region in the cell along the cell height direction, the second active region being the n-type or p-type opposite the n-type or p-type of the first active region and having a second total number of fins less than the first total number of fins and extending in the direction, and storing the IC layout diagram of the cell in a cell library.

公开(公告)号：US10678987B2

公开(公告)日：2020-06-09

申请号：US15793413

申请日：2017-10-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Sheng-Hsiung Chen ,  Fong-Yuan Chang

IPC: G06F30/30 ,  G06F30/392 ,  G06F30/39 ,  G06F111/20

Abstract: A method is disclosed. The method includes: obtaining a circuit design including a plurality of 2D cells of a 2D cell library; partitioning the plurality of 2D cells of the circuit design into a first group assigned to a first tier and a second group assigned to a second tier; swapping the 2D cells assigned to the first tier with corresponding 3D cells of a first type 3D cell library respectively; and swapping the 2D cells assigned to the second tier with corresponding 3D cells of a second type 3D cell library respectively; wherein at least one of the obtaining, partitioning, and swapping is performed using a processor. An associated system is also disclosed.

公开(公告)号：US09846759B2

公开(公告)日：2017-12-19

申请号：US14813483

申请日：2015-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Sheng-Hsiung Chen ,  Jyun-Hao Chang ,  Ting-Wei Chiang ,  Fong-Yuan Chang ,  I-Lun Tseng ,  Po-Hsiang Huang

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A method of global connection routing includes determining a global connection tolerance of a cell for use in a circuit layout, wherein the cell comprises a plurality of pins, and a plurality of routing tracks are defined with respect to the cell. The method further includes determining a number of blocked tracks within the cell. The method further includes comparing the global connection tolerance with the number of blocked tracks. The method further includes adjusting a location of the cell within the circuit layout if the global connection tolerance and the number of blocked tracks fail to satisfy a predetermined condition.

公开(公告)号：US12190034B2

公开(公告)日：2025-01-07

申请号：US18362938

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chi-Lin Liu ,  Jerry Chang-Jui Kao ,  Wei-Hsiang Ma ,  Lee-Chung Lu ,  Fong-Yuan Chang ,  Sheng-Hsiung Chen ,  Shang-Chih Hsieh

IPC: G06F30/327 ,  G06F111/06 ,  G06F119/18

Abstract: A logic circuit (for providing a multibit flip-flop (MBFF) function) includes: a first inverter to receive a clock signal and generate a corresponding clock_bar signal; a second inverter to receive the clock_bar signal and generate a corresponding clock_bar_bar signal; a third inverter to receive a control signal and generate a corresponding control_bar signal; and a series-chain of 1-bit transfer flip-flop (TXFF) circuits, each including: a NAND circuit to receive data signals; and a 1-bit transmit gate flip-flop (TGFF) circuit to output signals Q and q, and receive an output of the NAND circuit, the signal q from the TGFF circuit of a preceding TXFF circuit in the series-chain, the clock_bar and clock_bar_bar signals, and the control and control_bar signals; and the first transfer TXFF circuit in the series-chain being configured to receive a start signal in place of the signal q from an otherwise preceding TGFF circuit.

公开(公告)号：US12164854B2

公开(公告)日：2024-12-10

申请号：US17587381

申请日：2022-01-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ting-Chi Wang ,  Wai-Kei Mak ,  Kuan-Yu Chen ,  Hsiu-Chu Hsu ,  Hsuan-Han Liang ,  Sheng-Hsiung Chen

IPC: G06F30/392 ,  G06F30/327 ,  G06F30/396

Abstract: The present disclosure provides a method and an apparatus for arranging electrical components within a semiconductor device, and a non-transitory computer-readable medium. The method includes (a) placing a plurality of cells in a first layout; (b) generating a second layout by performing a first set of calculations on the first layout such that a total wire length of the second layout is less than that of the first layout; (c) generating a third layout by performing a second set of calculations on the second layout such that cell congestions in the second layout is eliminated from the third layout; (d) generating a fourth layout by performing a third set of calculations on the third layout such that the total wire length of the fourth layout is less than that of the third layout; and (e) iterating the operations (c) and (d) until a target layout conforms to a convergence criterion.

公开(公告)号：US12142637B2

公开(公告)日：2024-11-12

申请号：US17575590

申请日：2022-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Cheng-Yu Lin ,  Yi-Lin Fan ,  Hui-Zhong Zhuang ,  Sheng-Hsiung Chen ,  Jerry Chang Jui Kao ,  Xiangdong Chen

IPC: H01L29/06 ,  H01L23/522 ,  H01L29/40 ,  H01L29/423

Abstract: A cell region of a semiconductor device includes a first and second isolation dummy gates extending along a first direction. The semiconductor device further includes a first gate extending along the first direction and between the first isolation dummy gate and the second isolation dummy gate. The semiconductor device includes a second gate extending along the first direction, the second gate being between the first isolation dummy gate and the second isolation dummy gate relative to a second direction perpendicular to the first direction. The semiconductor device also includes a first active region and a second active region. The first active region extending in the second direction between the first isolation dummy gate and the second isolation dummy gate. The first active region has a first length in the second direction, and the second active region has a second length in the second direction different from the first length.