公开(公告)号：US12164854B2

公开(公告)日：2024-12-10

申请号：US17587381

申请日：2022-01-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ting-Chi Wang ,  Wai-Kei Mak ,  Kuan-Yu Chen ,  Hsiu-Chu Hsu ,  Hsuan-Han Liang ,  Sheng-Hsiung Chen

IPC: G06F30/392 ,  G06F30/327 ,  G06F30/396

Abstract: The present disclosure provides a method and an apparatus for arranging electrical components within a semiconductor device, and a non-transitory computer-readable medium. The method includes (a) placing a plurality of cells in a first layout; (b) generating a second layout by performing a first set of calculations on the first layout such that a total wire length of the second layout is less than that of the first layout; (c) generating a third layout by performing a second set of calculations on the second layout such that cell congestions in the second layout is eliminated from the third layout; (d) generating a fourth layout by performing a third set of calculations on the third layout such that the total wire length of the fourth layout is less than that of the third layout; and (e) iterating the operations (c) and (d) until a target layout conforms to a convergence criterion.

公开(公告)号：US11741286B2

公开(公告)日：2023-08-29

申请号：US17365531

申请日：2021-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Kai Hsu ,  Sheng-Hsiung Chen ,  Wai-Kei Mak ,  Ting-Chi Wang ,  Yu-Hsiang Cheng ,  Ding-Wei Huang

IPC: G06F30/392 ,  G03F1/70 ,  G06F30/398 ,  G06F111/04 ,  G06F30/31

CPC classification number: G06F30/392 ,  G03F1/70 ,  G06F30/398 ,  G06F30/31 ,  G06F2111/04

Abstract: A method (of generating a layout diagram) includes identifying, in the layout diagram, a group of three or more cells arranged so as to exhibit two or more edge-pairs (EPs) that are edge-wise abutted relative to a first direction. The method further includes, for each of at least one but fewer than all of the three or more cells, selectively moving a given one of cells corresponding to one of the members of the corresponding EP resulting in at least a minimum gap in the first direction between the members of the corresponding EP.

公开(公告)号：US10776551B2

公开(公告)日：2020-09-15

申请号：US16441802

申请日：2019-06-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Kai Hsu ,  Sheng-Hsiung Chen ,  Wai-Kei Mak ,  Ting-Chi Wang ,  Yu-Hsiang Cheng ,  Ding-Wei Huang

IPC: G06F30/392 ,  G06F30/398 ,  G03F1/70 ,  G06F111/04

Abstract: A method (of generating a layout diagram) includes: identifying, in the layout diagram, a group of three or more cells which violates a horizontal constraint vector (HCV) and is arranged so as to exhibit two or more vertically-aligned edge-pairs (VEPs); each VEP including two members representing at least partial portions of vertical edges of corresponding cells of the group; relative to a horizontal direction, the members of each VEP being disposed in edgewise-abutment and separated by a corresponding actual gap; and the HCV having separation thresholds, each of which has a corresponding VEP and represents a corresponding minimum gap in the horizontal direction between the members of the corresponding VEP; and for each of at least one but fewer than all of the separation thresholds, selectively moving a given one of cells corresponding to one of the members of the corresponding VEP thereby to avoid violating the HCV.

公开(公告)号：US11062076B2

公开(公告)日：2021-07-13

申请号：US16997703

申请日：2020-08-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Kai Hsu ,  Sheng-Hsiung Chen ,  Wai-Kei Mak ,  Ting-Chi Wang ,  Yu-Hsiang Cheng ,  Ding-Wei Huang

IPC: G06F30/392 ,  G06F30/398 ,  G03F1/70 ,  G06F30/31 ,  G06F111/04

Abstract: A method (of generating a layout diagram) includes: identifying, in the layout diagram, a group of three or more cells which violates a horizontal constraint vector (HCV) and is arranged so as to exhibit two or more vertically-aligned edge-pairs (VEPs); each VEP including two members representing at least partial portions of vertical edges of corresponding cells of the group; relative to a horizontal direction, the members of each VEP being disposed in edgewise-abutment and separated by a corresponding actual gap; and the HCV having separation thresholds, each of which has a corresponding VEP and represents a corresponding minimum gap in the horizontal direction between the members of the corresponding VEP; and for each of at least one but fewer than all of the separation thresholds, selectively moving a given one of cells corresponding to one of the members of the corresponding VEP thereby to avoid violating the HCV.

公开(公告)号：US10474038B2

公开(公告)日：2019-11-12

申请号：US15714141

申请日：2017-09-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Bo-Yang Chen ,  Chi-Chun Fang ,  Wai-Kei Mak ,  Ting-Chi Wang

IPC: G06F17/50 ,  G03F7/20 ,  G03F1/70 ,  H01L27/02 ,  H01L27/118

Abstract: A method performed by at least one processor includes: accessing a layout of an integrated circuit (IC), where the layout includes a plurality of patterns in one or more layers of the layout; performing a coloring operation; forming a list comprising at least one uncolorable cell group (UCG) of the layout based on a result of the coloring operation, where each of the at least one UCG comprises at least one uncolorable cell; and performing a first refinement for each UCG on the list. The first refinement is performed through: performing a movement on at least one uncolorable cell of the UCG; determining whether the UCG is colorable; and refining the layout by accepting the movement and removing the UCG from the list in response to the UCG being determined to be colorable.