公开(公告)号：US12164854B2

公开(公告)日：2024-12-10

申请号：US17587381

申请日：2022-01-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ting-Chi Wang ,  Wai-Kei Mak ,  Kuan-Yu Chen ,  Hsiu-Chu Hsu ,  Hsuan-Han Liang ,  Sheng-Hsiung Chen

IPC: G06F30/392 ,  G06F30/327 ,  G06F30/396

Abstract: The present disclosure provides a method and an apparatus for arranging electrical components within a semiconductor device, and a non-transitory computer-readable medium. The method includes (a) placing a plurality of cells in a first layout; (b) generating a second layout by performing a first set of calculations on the first layout such that a total wire length of the second layout is less than that of the first layout; (c) generating a third layout by performing a second set of calculations on the second layout such that cell congestions in the second layout is eliminated from the third layout; (d) generating a fourth layout by performing a third set of calculations on the third layout such that the total wire length of the fourth layout is less than that of the third layout; and (e) iterating the operations (c) and (d) until a target layout conforms to a convergence criterion.