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公开(公告)号:US11488842B2
公开(公告)日:2022-11-01
申请号:US16705334
申请日:2019-12-06
发明人: Chen-Yu Tsai , Tsung-Shang Wei , Yu-Sheng Lin , Wen-Chih Chiou , Shin-Puu Jeng
IPC分类号: H01L21/56 , H01L25/065 , H01L25/00 , H01L23/60 , H01L21/48 , H01L23/538 , H01L23/00 , H01L21/683 , H01L23/16 , H01L23/31 , H01L23/29 , H01L23/498
摘要: A method of manufacturing a semiconductor device includes bonding a first semiconductor die and a second semiconductor die to a first substrate, forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate, applying an encapsulant over the conductive layer, and removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer.
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公开(公告)号:US11444020B2
公开(公告)日:2022-09-13
申请号:US16846750
申请日:2020-04-13
发明人: Chen-Hua Yu , An-Jhih Su , Chi-Hsi Wu , Wen-Chih Chiou , Tsang-Jiuh Wu , Der-Chyang Yeh , Ming Shih Yeh
IPC分类号: H01L23/522 , H01L21/768 , H01L21/033 , H01L21/311 , H01L21/3105 , H01L21/683 , H01L21/02 , H01L23/00 , H01L23/528 , H01L33/62 , H01L21/56 , H01L25/075 , H01L33/38 , H01L25/07 , H01L23/538 , H01L33/00 , H01L33/06 , H01L33/32 , H01L21/321
摘要: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.
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公开(公告)号:US11037904B2
公开(公告)日:2021-06-15
申请号:US14950915
申请日:2015-11-24
发明人: Chen-Hua Yu , Tsang-Jiuh Wu , Wen-Chih Chiou
IPC分类号: H01L21/02 , H01L25/065 , H01L23/31 , H01L21/56 , H01L21/78 , H01L25/00 , H01L21/768
摘要: Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure.
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公开(公告)号:US20210005591A1
公开(公告)日:2021-01-07
申请号:US17029065
申请日:2020-09-23
发明人: Yu-Kuang Liao , Cheng-Chun Tsai , Chen-Hua Yu , Fang-Cheng Chen , Wen-Chih Chiou , Ping-Jung Wu
摘要: A semiconductor package includes a first optical transceiver, a second optical transceiver, a third optical transceiver, and a plasmonic waveguide. The first optical transceiver, the second optical transceiver, and the third optical transceiver are stacked in sequential order. The first optical transceiver and the third optical transceiver respectively at least one optical input/output portion for transmitting and receiving an optical signal. The plasmonic waveguide includes a first segment, a second segment, and a third segment optically coupled to one another. The first segment is embedded in the first optical transceiver. The second segment extends through the second optical transceiver. The third segment is embedded in the third optical transceiver. The first segment is optically coupled to the at least one optical input/output portion of the first optical transceiver and the third segment is optically coupled to the at least one optical input/output portion of the third optical transceiver.
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公开(公告)号:US10854567B2
公开(公告)日:2020-12-01
申请号:US16716811
申请日:2019-12-17
发明人: Shang-Yun Hou , Sao-Ling Chiu , Ping-Kang Huang , Wen-Hsin Wei , Wen-Chih Chiou , Shin-Puu Jeng , Bruce C. S. Chou
IPC分类号: H01L23/498 , H01L23/00 , H01L25/00 , H01L21/44 , H01L23/522 , H01L21/304 , H01L21/306 , H01L21/56 , H01L23/31
摘要: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method comprising forming a conductive pad in a first substrate, forming an interconnecting structure over the conductive pad and the first substrate, the interconnecting structure comprising a plurality of metal layers disposed in a plurality of dielectric layers, bonding a die to a first side of the interconnecting structure, and etching the first substrate from a second side of the interconnecting structure, the etching exposing a portion of the conductive pad.
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公开(公告)号:US10727294B2
公开(公告)日:2020-07-28
申请号:US15883746
申请日:2018-01-30
发明人: Wen-Chih Chiou , Shin-Puu Jeng , Ebin Liao
IPC分类号: H01L49/02 , H01L23/522 , H01L23/525 , H01L23/532 , H01L27/02 , H01L27/08
摘要: Semiconductor devices, methods of manufacture thereof, and capacitors are disclosed. In some embodiments, a semiconductor device includes a first capacitor and a protection device coupled in series with the first capacitor. A second capacitor is coupled in parallel with the first capacitor and the protection device.
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公开(公告)号:US20200126938A1
公开(公告)日:2020-04-23
申请号:US16716811
申请日:2019-12-17
发明人: Shang-Yun Hou , Sao-Ling Chiu , Ping-Kang Huang , Wen-Hsin Wei , Wen-Chih Chiou , Shin-Puu Jeng , Bruce C.S. Chou
IPC分类号: H01L23/00 , H01L23/522 , H01L23/31 , H01L21/56 , H01L21/306 , H01L21/304 , H01L23/498 , H01L21/44 , H01L25/00
摘要: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method comprising forming a conductive pad in a first substrate, forming an interconnecting structure over the conductive pad and the first substrate, the interconnecting structure comprising a plurality of metal layers disposed in a plurality of dielectric layers, bonding a die to a first side of the interconnecting structure, and etching the first substrate from a second side of the interconnecting structure, the etching exposing a portion of the conductive pad.
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公开(公告)号:US10535586B2
公开(公告)日:2020-01-14
申请号:US16402603
申请日:2019-05-03
发明人: Yung-Chi Lin , Tsang-Jiuh Wu , Wen-Chih Chiou
IPC分类号: H01L23/48 , H01L21/768
摘要: Methods and apparatus entailing an interconnect structure comprising interconnect features disposed in dielectric material over a substrate. Each interconnect feature comprises an interconnect member and a via extending between the interconnect member and a conductive member formed within the dielectric material. A through-silicon-via (TSV) structure is formed laterally offset from the interconnect structure by forming a first portion of the TSV structure with a first conductive material and forming a second portion of the TSV structure with a second conductive material. Forming the second portion of the TSV structure occurs substantially simultaneously with forming one of the interconnect features.
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公开(公告)号:US20190252312A1
公开(公告)日:2019-08-15
申请号:US16121360
申请日:2018-09-04
发明人: Chen-Hua Yu , An-Jhih Su , Chi-Hsi Wu , Wen-Chih Chiou , Tsang-Jiuh Wu , Der-Chyang Yeh , Ming Shih Yeh
IPC分类号: H01L23/522 , H01L23/00 , H01L21/768 , H01L21/033 , H01L21/311 , H01L21/3105 , H01L21/683 , H01L21/02 , H01L23/528 , H01L33/00 , H01L33/62 , H01L21/56 , H01L25/075 , H01L33/38
CPC分类号: H01L23/5226 , H01L21/02271 , H01L21/0228 , H01L21/0332 , H01L21/0337 , H01L21/31053 , H01L21/31111 , H01L21/3212 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/76802 , H01L21/76819 , H01L21/76837 , H01L21/7684 , H01L21/76843 , H01L21/76877 , H01L23/528 , H01L24/05 , H01L24/11 , H01L24/81 , H01L24/89 , H01L25/0753 , H01L33/007 , H01L33/0079 , H01L33/06 , H01L33/32 , H01L33/38 , H01L33/62 , H01L2221/68359 , H01L2221/68363 , H01L2221/68381 , H01L2224/03002 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/03622 , H01L2224/08225 , H01L2224/08501 , H01L2224/80006 , H01L2224/80815 , H01L2224/80895 , H01L2224/81005 , H01L2224/81815 , H01L2924/01022 , H01L2924/01029 , H01L2924/12041 , H01L2933/0016 , H01L2933/0025 , H01L2933/005 , H01L2933/0066
摘要: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.
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公开(公告)号:US20190244851A1
公开(公告)日:2019-08-08
申请号:US16390248
申请日:2019-04-22
发明人: Yan-Zuo Tsai , Yang-Chih Hsueh , Chia-Yin Chen , Fu-Kang Tien , Ebin Liao , Wen-Chih Chiou
IPC分类号: H01L21/683 , H01L23/00 , H01L21/66
摘要: A method and apparatus for bonding semiconductor devices are disclosed. In an embodiment, the method may include attaching a first die to a flip head of a flip module, flipping the first die with the flip module, removing the first die from the flip module after flipping the first die, inspecting the flip head of the flip module for contamination after removing the first die, cleaning the flip head with an in situ cleaning module after inspecting the flip head, and attaching a second die to the flip head after cleaning the flip head.
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