公开(公告)号：US20240220761A1

公开(公告)日：2024-07-04

申请号：US18517942

申请日：2023-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngwoo Park

IPC: G06K19/077 ,  G06K19/06

CPC classification number: G06K19/07747 ,  G06K19/06121 ,  G06K19/07732 ,  G06K19/07743

Abstract: A memory card includes a case including a first case portion and a second case portion that is coupled to the first case portion, an integrated circuit package located in the case, and a marking layer located in the case, wherein the second case portion includes a through-hole, wherein the marking layer is exposed to an outside through the through-hole.

公开(公告)号：US20240125841A1

公开(公告)日：2024-04-18

申请号：US18454404

申请日：2023-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheongwon Lee ,  Gyosoo Choo ,  Youngwoo Park ,  Seunghoon Lee ,  Jinwoo Choi

IPC: G01R31/26

CPC classification number: G01R31/2607

Abstract: An embodiment provides a test element group (TEG) circuit, including: a first pad configured for a test voltage to be applied; an amplifier including a first input terminal connected to the first pad, a second input terminal connected to a first terminal of a test transistor, and an output terminal electrically connected to the second input terminal; a variable resistor including one terminal connected to the output terminal of the amplifier and the other terminal connected to the first terminal of the test transistor; and a gate driving circuit that supplies a gate voltage to a gate of the test transistor.

公开(公告)号：US11785732B2

公开(公告)日：2023-10-10

申请号：US17227043

申请日：2021-04-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngwoo Park

IPC: H05K5/02 ,  H01L25/18 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K5/026 ,  H01L25/18 ,  H05K1/0271 ,  H05K1/18 ,  H05K2201/09027 ,  H05K2201/10159

Abstract: A memory card includes a case and an integrated circuit package disposed in the case. The case includes a first case edge, a second case edge connected to the first case edge, a third case edge connected to the second case edge, a fourth case edge connected to the third case edge and the first case edge, and a first recessed groove formed in the second case edge, the first recessed groove being spaced apart from the first case edge and inwardly recessed. The integrated circuit package is disposed in an upper portion of the case between the first case edge and a first horizontal line that extends in a direction from a top end of the first recessed groove in the second case edge to the fourth case edge.

公开(公告)号：US10566233B2

公开(公告)日：2020-02-18

申请号：US16534195

申请日：2019-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohyun Lee ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

IPC: H01L21/00 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573 ,  H01L23/532 ,  H01L23/522 ,  H01L27/1157 ,  H01L23/528

Abstract: A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

公开(公告)号：US09685452B2

公开(公告)日：2017-06-20

申请号：US15245218

申请日：2016-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun Lee ,  Heonkyu Lee ,  Shinhwan Kang ,  Youngwoo Park

IPC: H01L27/115 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11582 ,  H01L23/535

CPC classification number: H01L27/11582 ,  H01L23/5283 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including electrodes vertically stacked on a substrate, a channel structure coupled to the electrodes to constitute a plurality of memory cells three-dimensionally arranged on the substrate, the channel structure including first vertical channels and second vertical channels penetrating the stack structure and a first horizontal channel disposed under the stack structure to laterally connect the first vertical channels and the second vertical channels to each other, a second horizontal channel having a first conductivity type and connected to a sidewall of the first horizontal channel of the channel structure, and conductive plugs having a second conductivity type and disposed on top ends of the second vertical channels.

公开(公告)号：US09559112B2

公开(公告)日：2017-01-31

申请号：US14472952

申请日：2014-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaegoo Lee ,  Youngwoo Park ,  Jungdal Choi

IPC: H01L27/115 ,  H01L29/78 ,  H01L29/423 ,  H01L29/792

CPC classification number: H01L27/11578 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/7827 ,  H01L29/7926

Abstract: A method of fabricating a semiconductor memory device includes forming a mold stack on a substrate and the mold stack including first sacrificial layers and second sacrificial layers alternately stacked on the substrate. The method also includes forming a plurality of vertical channels that penetrate the mold stack and that contact the substrate, patterning the mold stack to form word line cuts between the vertical channels, the word line cuts exposing the substrate, removing one of the first and second sacrificial layers to form recessed regions in the mold stack, forming a data storage layer, at least a portion of the data storage layer being formed between the vertical channels and the gates, forming gates in the recessed regions, forming air gaps between the gates by removing the other of the first and second sacrificial layers, and forming an insulation layer pattern in the word line cuts.

Abstract translation: 一种制造半导体存储器件的方法包括在衬底上形成模具堆叠，并且模具叠层包括交替层叠在衬底上的第一牺牲层和第二牺牲层。 该方法还包括形成多个垂直通道，其穿过模具叠层并与衬底接触，图案化模具叠层以形成垂直通道之间的字线切口，字线切割暴露衬底，去除第一和第二 牺牲层，以在模具堆叠中形成凹陷区域，形成数据存储层，数据存储层的至少一部分形成在垂直沟道和栅极之间，在凹陷区域中形成栅极，在栅极之间形成气隙，通过 去除第一和第二牺牲层中的另一个，并且在字线切割中形成绝缘层图案。

公开(公告)号：US09515087B2

公开(公告)日：2016-12-06

申请号：US14878453

申请日：2015-10-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunghwan Son ,  Jaesung Sim ,  Shinhwan Kang ,  Youngwoo Park ,  Jaeduk Lee

IPC: G11C5/02 ,  H01L27/115 ,  G11C16/30 ,  H01L29/34 ,  G11C16/04

CPC classification number: H01L27/11575 ,  G11C5/025 ,  G11C16/0483 ,  G11C16/30 ,  H01L27/11517 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/34

Abstract: A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.

Abstract translation: 一种三维（3D）半导体存储器件，其包括外围逻辑结构，该外围逻辑结构包括设置在半导体衬底上的外围逻辑电路和与外围逻辑电路重叠的第一绝缘层，以及在周边彼此间隔开的多个存储块 逻辑结构。 存储块中的至少一个包括阱板电极，与阱板电极的第一表面接触的半导体层，包括垂直堆叠在半导体层上的多个电极的堆叠结构，以及穿透 堆叠结构并连接到半导体层。

公开(公告)号：US09437483B2

公开(公告)日：2016-09-06

申请号：US14218091

申请日：2014-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegoo Lee ,  Youngwoo Park

IPC: H01L21/4763 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L21/76832 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

Abstract: A plurality of vertical channels of semiconductor material are formed to extend in a vertical direction through the plurality of insulation layers and the plurality of conductive patterns, a gate insulating layer between the conductive pattern and the vertical channels that insulates the conductive pattern from the vertical channels. Conductive contact regions of the at least two of the conductive patterns are in a stepped configuration. An etch stop layer is positioned on the conductive contact regions, wherein the etch stop layer has a first portion on a first one of the plurality of conductive patterns and has a second portion on a second one of the plurality of conductive patterns, wherein the first portion is of a thickness that is greater than a thickness of the second portion.

Abstract translation: 多个垂直通道的半导体材料形成为沿着垂直方向延伸穿过多个绝缘层和多个导电图案，导电图案和垂直沟道之间的栅极绝缘层将导电图案与垂直沟道绝缘 。 至少两个导电图案的导电接触区域处于阶梯状结构。 蚀刻停止层位于导电接触区域上，其中蚀刻停止层在多个导电图案中的第一个上具有第一部分，并且在多个导电图案中的第二个导电图案上具有第二部分，其中第一部分 部分的厚度大于第二部分的厚度。

公开(公告)号：US20130301340A1

公开(公告)日：2013-11-14

申请号：US13796808

申请日：2013-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINTAEK PARK ,  Youngwoo Park ,  Jungdal Choi

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C13/0064 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/78 ,  G11C2213/79

Abstract: An erase method of a resistive random access memory which includes a plurality of cell strings, each having a plurality of memory cells and a string selection transistor, includes applying a first voltage to bit lines connected with string selection transistors of the plurality of cell strings, applying a turn-on voltage to at least one string selection line selected from string selection lines connected with the string selection transistors, applying a turn-off voltage to unselected string selection lines of the string selection lines, applying a second voltage to at least one word line selected from word lines connected with memory cells of the plurality of cell strings, and floating unselected word lines of the word lines.

Abstract translation: 一种电阻随机存取存储器的擦除方法，包括多个单元串，每个单元串具有多个存储单元和串选择晶体管，包括将第一电压施加到与多个单元串中的串选择晶体管连接的位线， 对从与串选择晶体管连接的串选择线中选择的至少一个串选择线施加接通电压，向串选择线的未选择的串选择线施加截止电压，将第二电压施加到至少一个 从与多个单元串中的存储单元相连的字线选择的字线和字线的浮动未选字线。

公开(公告)号：US20250166677A1

公开(公告)日：2025-05-22

申请号：US18785979

申请日：2024-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jichull Jeong ,  Youngwoo Park ,  Seungjin Park ,  Jindo Byun ,  Seunghoon Lee ,  Eunsang Lee ,  Chaekang Lim

IPC: G11C7/14 ,  G11C7/06 ,  G11C7/10

Abstract: Disclosed is a memory device which includes a driver unit that includes a pull-up driver and a pull-down driver, a ZQ calibration unit that performs ZQ calibration with respect to the driver unit based on an external resistor and a first reference voltage and generates a first ZQ code corresponding to the first reference voltage, and a code conversion unit that generates a second ZQ code corresponding to a second reference voltage different from the first reference voltage, based on the first ZQ code.