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    SIMULATION METHOD AND SYSTEM
    12.
    发明申请
    SIMULATION METHOD AND SYSTEM 审中-公开

    公开(公告)号：US20200342157A1

    公开(公告)日：2020-10-29

    申请号：US16794045

    申请日：2020-02-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Alexander SCHMIDT ,  Dong-Gwan SHIN ,  Anthony PAYET ,  Hyoung Soo KO ,  Seok Hoon KIM ,  Hyun-Kwan YU ,  Si Hyung LEE ,  In Kook JANG

    IPC: G06F30/398 ,  H01L27/02 ,  G06F30/367

    Abstract: A simulation method and system which can determine a predictable epitaxy time by accurately reflecting layout characteristics of a chip and characteristics of a source/drain formation process are provided. The simulation method includes storing a plurality of structure parameters of transistors for a semiconductor chip, the structure parameters determined by using imaging equipment, generating a first local layout which includes a first structure parameter extracted from a semiconductor device included in the first local layout, the first structure parameter being an actual parameter determined using the imaging equipment, generating second to n-th local layouts by modifying the first structure parameter included in the first local layout, wherein the second to n-th local layouts respectively have second to n-th structure parameters modified from the first structure parameter, calculating first to n-th effective density factors(EDF) respectively for the first to n-th structure parameters using a predetermined simulation of the first to n-th structure parameters, determining a first effective open silicon density for a first chip using the first to n-th effective density factors and a layout of the first chip, and calculating a first epitaxy time for the first effective open silicon density, calculating second to m-th epitaxy times for second to m-th effective open silicon densities, and performing a regression analysis of effective open silicon density versus epitaxy time based on the calculation result, where n is a natural number equal to or greater than 3, and m is a natural number equal to or greater than 3.

    SEMICONDUCTOR DEVICE
    14.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240332424A1

    公开(公告)日：2024-10-03

    申请号：US18740736

    申请日：2024-06-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yang XU ,  Nam Kyu CHO ,  Seok Hoon KIM ,  Yong Seung KIM ,  Pan Kwi PARK ,  Dong Suk SHIN ,  Sang Gil LEE ,  Si Hyung LEE

    IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417

    CPC classification number: H01L29/7851 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41791

    Abstract: A semiconductor device including first fin-shaped patterns in a first region of a substrate and spaced apart from each other in a first direction, second fin-shaped patterns in a second region of the substrate and spaced apart from each other in a second direction, a first field insulating film on the substrate and covering sidewalls of the first fin-shaped patterns, a second field insulating film on the substrate and covering sidewalls of the second fin-shaped patterns, a first source/drain pattern on the first field insulating film, connected to the first fin-shaped patterns, and including a first silicon-germanium pattern, and a second source/drain pattern on the second field insulating film, connected to the second fin-shaped patterns, and including a second silicon-germanium pattern, the second source/drain pattern and the second field insulating film defining one or more first air gaps therebetween may be provided.

    SEMICONDUCTOR DEVICE
    16.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230058991A1

    公开(公告)日：2023-02-23

    申请号：US17690178

    申请日：2022-03-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yang XU ,  Nam Kyu CHO ,  Seok Hoon KIM ,  Yong Seung KIM ,  Pan Kwi PARK ,  Dong Suk SHIN ,  Sang Gil LEE ,  Si Hyung LEE

    IPC: H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L29/06

    Abstract: A semiconductor device including first fin-shaped patterns in a first region of a substrate and spaced apart from each other in a first direction, second fin-shaped patterns in a second region of the substrate and spaced apart from each other in a second direction, a first field insulating film on the substrate and covering sidewalls of the first fin-shaped patterns, a second field insulating film on the substrate and covering sidewalls of the second fin-shaped patterns, a first source/drain pattern on the first field insulating film, connected to the first fin-shaped patterns, and including a first silicon-germanium pattern, and a second source/drain pattern on the second field insulating film, connected to the second fin-shaped patterns, and including a second silicon-germanium pattern, the second source/drain pattern and the second field insulating film defining one or more first air gaps therebetween may be provided.

    SEMICONDUCTOR DEVICE
    17.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220181498A1

    公开(公告)日：2022-06-09

    申请号：US17391342

    申请日：2021-08-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung Taek KIM ,  Seok Hoon KIM ,  Ryong HA ,  Pan Kwi PARK ,  Dong Suk SHIN

    IPC: H01L29/786 ,  H01L29/66

    Abstract: There is provided a semiconductor device comprising an active pattern, including a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction perpendicular to the first direction, a plurality of gate structures on the lower pattern to be spaced apart from each other in the first direction and including a gate electrode and a gate insulating film wrapping the plurality of sheet patterns, a source/drain recess defined between the gate structures adjacent to each other, and a source/drain pattern inside the source/drain recess and including a semiconductor blocking film formed continuously along the source/drain recess, wherein the source/drain recesses include a plurality of width extension regions, and a width of each of the width extension regions in the first direction increases and then decreases, as it goes away from an upper surface of the lower pattern.

    SEMICONDUCTOR DEVICE
    18.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210159246A1

    公开(公告)日：2021-05-27

    申请号：US17144458

    申请日：2021-01-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Namkyu Edward CHO ,  Seok Hoon KIM ,  Myung Il KANG ,  Geo Myung SHIN ,  Seung Hun LEE ,  Jeong Yun LEE ,  Min Hee CHOI ,  Jeong Min CHOI

    IPC: H01L27/11582 ,  H01L29/66 ,  H01L21/768 ,  H01L29/78

    Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.

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