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    Integrated circuit device and method of manufacturing the same
    15.
    发明授权
    Integrated circuit device and method of manufacturing the same 有权

    公开(公告)号：US11069613B2

    公开(公告)日：2021-07-20

    申请号：US16742233

    申请日：2020-01-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Woojin Lee ,  Junghoo Shin ,  Sanghoon Ahn ,  Junhyuk Lim ,  Daehan Kim

    IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/485

    Abstract: An integrated circuit device includes a first insulation layer on a substrate, a lower wiring structure in the first insulation layer and including a metal layer and a conductive barrier layer, such that the metal layer is on the conductive barrier layer, an etch stop layer overlapping an upper surface of the first insulation layer and an upper surface of the conductive barrier layer and having a first thickness, a capping layer overlapping a portion of the upper surface of the metal layer and having a second thickness which is less than the first thickness, a second insulation layer overlapping the etch stop layer and the capping layer, and an upper wiring structure connected to another portion of the upper surface of the metal layer not overlapped by the capping layer in the second insulation layer.

    Semiconductor device and method of manufacturing the same
    16.
    发明授权
    Semiconductor device and method of manufacturing the same 有权

    公开(公告)号：US10943824B2

    公开(公告)日：2021-03-09

    申请号：US16411439

    申请日：2019-05-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Woojin Lee ,  Hoon Seok Seo ,  Sanghoon Ahn ,  Kyu-Hee Han

    IPC: H01L23/528 ,  H01L21/768

    Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

    Semiconductor devices including a capping layer
    17.
    发明授权
    Semiconductor devices including a capping layer 有权

    公开(公告)号：US10707164B2

    公开(公告)日：2020-07-07

    申请号：US16296388

    申请日：2019-03-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sangho Rha ,  Jongmin Baek ,  Wookyung You ,  Sanghoon Ahn ,  Nae-In Lee

    IPC: H01L23/528 ,  H01L21/306 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/288 ,  H01L21/321

    Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.

    Semiconductor device
    18.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10566284B2

    公开(公告)日：2020-02-18

    申请号：US16027484

    申请日：2018-07-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jun Kwan Kim ,  Sanghoon Ahn ,  Kyu-Hee Han ,  JaeWha Park ,  Heesook Park

    IPC: H01L23/532 ,  H01L23/522

    Abstract: Provided is a semiconductor device comprising a device region on a substrate, an interlayer dielectric layer on the device region, a first interface layer on a side of the interlayer dielectric layer, a low-k dielectric layer spaced apart from the interlayer dielectric layer across the first interface layer and having a dielectric constant less than that of the interlayer dielectric layer, and a conductive line in the low-k dielectric layer. The first interface layer comprises a first sub-interface layer in contact with the low-k dielectric layer, and a second sub-interface layer in contact with the interlayer dielectric layer. The second sub-interface layer has hydrogen permeability less than that of the first sub-interface layer.

    Semiconductor devices having staggered air gaps
    19.
    发明授权
    Semiconductor devices having staggered air gaps 有权

    公开(公告)号：US10141258B2

    公开(公告)日：2018-11-27

    申请号：US15659125

    申请日：2017-07-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sangho Rha ,  Jongmin Baek ,  Wookyung You ,  Sanghoon Ahn ,  Naein Lee

    IPC: H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/764

    Abstract: A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween. The air gaps may include first air gaps, and the device may further include second air gaps disposed between adjacent ones of the second conductive patterns in the second region. Adjacent ones of the second conductive patterns overlying a second region of the substrate may not have air gaps disposed therebetween.

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