公开(公告)号：US10734280B2

公开(公告)日：2020-08-04

申请号：US16154896

申请日：2018-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-hyuk Yim ,  Kuo Tai Huang ,  Wan-don Kim ,  Sang-jin Hyun

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L29/417 ,  H01L23/532 ,  H01L29/78

Abstract: An integrated circuit (IC) device includes a substrate having a fin-type active region extending in a first direction, a gate structure intersecting the fin-type active region on the substrate, the gate structure extending in a second direction perpendicular to the first direction and parallel to a top surface of the substrate, source and drain regions on both sides of the gate structure, and a first contact structure electrically connected to one of the source and drain regions, the first contact structure including a first contact plug including a first material and a first wetting layer surrounding the first contact plug, the first wetting layer including a second material having a lattice constant that differs from a lattice constant of the first material by about 10% or less.

公开(公告)号：US20200168720A1

公开(公告)日：2020-05-28

申请号：US16552150

申请日：2019-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-young Kwak ,  Ji-ye Kim ,  Jung-hwan Chun ,  Min-chan Gwak ,  Dong-hyun Roh ,  Jin-wook Lee ,  Sang-jin Hyun

IPC: H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L29/45 ,  H01L29/78 ,  H01L21/8238

Abstract: An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.

公开(公告)号：US10593670B2

公开(公告)日：2020-03-17

申请号：US15697720

申请日：2017-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-yeol Song ,  Wan-don Kim ,  Oh-seong Kwon ,  Hyeok-jun Son ,  Sang-jin Hyun ,  Hoon-joo Na

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

Abstract: Integrated circuit devices include a substrate including first and second fin-type active regions and first and second gate structures. The first gate structure includes first gate insulating layer on the first fin-type active region to cover upper surface and both side surfaces of the first fin-type active region, first gate electrode on the first gate insulating layer and has first thickness in first direction perpendicular to upper surface of the substrate, and second gate electrode on the first gate electrode. The second gate structure includes second gate insulating layer on the second fin-type active region to cover upper surface and both side surfaces of the second fin-type active region, third gate insulating layer on the second gate insulating layer, third gate electrode on the third gate insulating layer and has second thickness different from the first thickness in the first direction, and fourth gate electrode on the third gate electrode.

公开(公告)号：US10529816B2

公开(公告)日：2020-01-07

申请号：US15915508

申请日：2018-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-hyeong Lee ,  Hoon-joo Na ,  Sung-in Suh ,  Min-woo Song ,  Byoung-hoon Lee ,  Hu-yong Lee ,  Sang-jin Hyun

IPC: H01L29/772 ,  H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/28 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device includes an active region in a substrate, at least one nano-sheet on the substrate and spaced apart from a top surface of the active region, a gate above or below the nano-sheet, a gate insulating layer between the at least one nano-sheet and the gate, and source/drain regions on the active region at both sides of the at least one nano-sheet. The at least one nano-sheet includes a channel region; a gate disposed above or below the nano-sheet and including a single metal layer having different compositions of metal atoms of a surface and an inside thereof; a gate insulating layer between the nano-sheet and the gate; and source/drain regions disposed in the active region of both sides of the at least one nano-sheet.

公开(公告)号：US20190189767A1

公开(公告)日：2019-06-20

申请号：US16042114

申请日：2018-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-yeol SONG ,  Wan-don Kim ,  Su-young Bae ,  Dong-soo Lee ,  Jong-han Lee ,  Hyung-suk Jung ,  Sang-jin Hyun

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/51 ,  H01L21/8234

Abstract: A semiconductor device includes active regions on a semiconductor substrate, gate structures on separate, respective active regions, and source/drain regions in the semiconductor substrate on opposite sides of separate, respective gate structures. Each separate gate structure includes a sequential stack of a high dielectric layer, a first work function metal layer, a second work function metal layer having a lower work function than the first work function metal layer, and a gate metal layer. First work function metal layers of the gate structures have different thicknesses, such that the gate structures include a largest gate structure where the first work function metal layer of the largest gate structure has a largest thickness of the first work function metal layers. The largest gate structure includes a capping layer on the high dielectric layer of the largest gate structure, where the capping layer includes one or more impurity elements.

公开(公告)号：US09929252B2

公开(公告)日：2018-03-27

申请号：US15133548

申请日：2016-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-gyu Choi ,  Sang-jin Hyun ,  Taek-soo Jeon ,  Hoon-joo Na ,  Young-suk Chai

IPC: H01L29/66 ,  H01L21/324 ,  H01L21/02 ,  C23C16/02 ,  C23C16/40

CPC classification number: H01L29/66795 ,  C23C16/0218 ,  C23C16/405 ,  H01L21/02236 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/02312 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/28255 ,  H01L21/324 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/78642

Abstract: A method of forming a thin film includes forming an interface layer stack on a semiconductor substrate. Forming the interface layer stack may include performing a first surface treatment on the semiconductor substrate under a reducing atmosphere. Forming the interface layer stack may include performing a second surface treatment on the semiconductor substrate. The first surface treatment may be performed under a reducing atmosphere and the second surface treatment may be performed under a nitridation atmosphere. The first surface treatment may include forming a lower interface layer on a surface of the semiconductor substrate and the second surface treatment may include forming an upper interface layer. The first surface treatment may include selectively removing at least one oxide material from a native oxide film on the semiconductor substrate.

公开(公告)号：US09806075B2

公开(公告)日：2017-10-31

申请号：US15001283

申请日：2016-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-yeol Song ,  Wan-don Kim ,  Oh-seong Kwon ,  Hyeok-jun Son ,  Sang-jin Hyun ,  Hoon-joo Na

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L29/0653 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: Integrated circuit devices include a substrate including first and second fin-type active regions and first and second gate structures. The first gate structure includes first gate insulating layer on the first fin-type active region to cover upper surface and both side surfaces of the first fin-type active region, first gate electrode on the first gate insulating layer and has first thickness in first direction perpendicular to upper surface of the substrate, and second gate electrode on the first gate electrode. The second gate structure includes second gate insulating layer on the second fin-type active region to cover upper surface and both side surfaces of the second fin-type active region, third gate insulating layer on the second gate insulating layer, third gate electrode on the third gate insulating layer and has second thickness different from the first thickness in the first direction, and fourth gate electrode on the third gate electrode.

公开(公告)号：US09240483B2

公开(公告)日：2016-01-19

申请号：US13684655

申请日：2012-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： June-hee Lee ,  Jae-yeol Song ,  Hye-Ian Lee ,  Hong-bae Park ,  Sang-jin Hyun

IPC: H01L21/70 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/785 ,  H01L27/0886

Abstract: A semiconductor device includes a fin-type active region; a gate dielectric layer covering an upper surface and opposite lateral surfaces of the fin-type active region; and a gate line extending on the gate dielectric layer to cover the upper surface and opposite lateral surfaces of the fin-type active region and to cross the fin-type active region. The gate line includes an aluminum (Al) doped metal-containing layer extending to cover the upper surface and opposite lateral surfaces of the fin-type active region to a uniform thickness, and a gap-fill metal layer extending on the Al doped metal-containing layer over the fin-type active region. Related fabrication methods are also described.

Abstract translation: 半导体器件包括鳍型有源区; 覆盖所述鳍状有源区的上表面和相对的侧表面的栅介电层; 以及在所述栅极电介质层上延伸以覆盖所述鳍状有源区的上表面和相对的侧表面并跨越所述鳍型有源区的栅极线。 栅极线包括铝（Al）掺杂的含金属层，其延伸以覆盖翅片型有源区的上表面和相对的侧表面至均匀的厚度;以及间隙填充金属层，其在Al掺杂的金属 - 在翅片型有源区域上方。 还描述了相关的制造方法。

公开(公告)号：US20130277748A1

公开(公告)日：2013-10-24

申请号：US13684655

申请日：2012-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： June-Hee LEE ,  Jae-yeol Song ,  Hye-Ian Lee ,  Hong-bae Park ,  Sang-jin Hyun

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L27/0886

Abstract: A semiconductor device includes a fin-type active region; a gate dielectric layer covering an upper surface and opposite lateral surfaces of the fin-type active region; and a gate line extending on the gate dielectric layer to cover the upper surface and opposite lateral surfaces of the fin-type active region and to cross the fin-type active region. The gate line includes an aluminum (Al) doped metal-containing layer extending to cover the upper surface and opposite lateral surfaces of the fin-type active region to a uniform thickness, and a gap-fill metal layer extending on the Al doped metal-containing layer over the fin-type active region. Related fabrication methods are also described.

Abstract translation: 半导体器件包括鳍型有源区; 覆盖所述鳍状有源区的上表面和相对的侧表面的栅介电层; 以及在所述栅极电介质层上延伸以覆盖所述鳍状有源区的上表面和相对的侧表面并跨越所述鳍型有源区的栅极线。 栅极线包括铝（Al）掺杂的含金属层，其延伸以覆盖翅片型有源区的上表面和相对的侧表面至均匀的厚度;以及间隙填充金属层，其在Al掺杂的金属 - 在翅片型有源区域上方。 还描述了相关的制造方法。