公开(公告)号：US09929252B2

公开(公告)日：2018-03-27

申请号：US15133548

申请日：2016-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-gyu Choi ,  Sang-jin Hyun ,  Taek-soo Jeon ,  Hoon-joo Na ,  Young-suk Chai

IPC: H01L29/66 ,  H01L21/324 ,  H01L21/02 ,  C23C16/02 ,  C23C16/40

CPC classification number: H01L29/66795 ,  C23C16/0218 ,  C23C16/405 ,  H01L21/02236 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/02312 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/28255 ,  H01L21/324 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/78642

Abstract: A method of forming a thin film includes forming an interface layer stack on a semiconductor substrate. Forming the interface layer stack may include performing a first surface treatment on the semiconductor substrate under a reducing atmosphere. Forming the interface layer stack may include performing a second surface treatment on the semiconductor substrate. The first surface treatment may be performed under a reducing atmosphere and the second surface treatment may be performed under a nitridation atmosphere. The first surface treatment may include forming a lower interface layer on a surface of the semiconductor substrate and the second surface treatment may include forming an upper interface layer. The first surface treatment may include selectively removing at least one oxide material from a native oxide film on the semiconductor substrate.

公开(公告)号：US08928152B2

公开(公告)日：2015-01-06

申请号：US14186025

申请日：2014-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taek-soo Jeon ,  Bong-hyun Kim ,  Won-seok Yoo ,  Jae-hong Seo ,  Ho-kyun An ,  Dae-hyun Kim

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/10 ,  H01L21/768 ,  H01L23/522 ,  H01L27/108 ,  H01L21/285

CPC classification number: H01L23/5226 ,  H01L21/28525 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/10823 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate having a conductive area, a first pattern formed on the substrate and having a contact hole through which the conductive area is exposed, and a contact plug in the contact hole. The contact plug includes first and second silicon layers. The first silicon layer, formed from a first compound including at least two silicon atoms, is formed in the contact hole to contact a top surface of the conductive area and a side wall of the first pattern. The second silicon layer, formed from a second compound including a number of silicon atoms less than the number of the silicon atoms of the first compound, is formed on the first silicon layer and fills a remaining space of the contact hole, the second silicon layer being spaced apart from the first pattern at an entrance of the contact hole.

Abstract translation: 半导体器件包括具有导电区域的基板，形成在基板上的第一图案，具有导电区域露出的接触孔和接触孔中的接触插塞。 接触插塞包括第一和第二硅层。 在包括至少两个硅原子的第一化合物形成的第一硅层形成在接触孔中以接触导电区域的顶表面和第一图案的侧壁。 在第一硅层上形成由第二化合物构成的第二硅层，该第二化合物包含少于第一化合物的硅原子数的硅原子数，并填充接触孔的剩余空间，第二硅层 在接触孔的入口处与第一图案间隔开。

公开(公告)号：US20140167288A1

公开(公告)日：2014-06-19

申请号：US14186025

申请日：2014-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taek-soo Jeon ,  Bong-hyun Kim ,  Won-seok Yoo ,  Jae-hong Seo ,  Ho-kyun An ,  Dae-hyun Kim

IPC: H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/28525 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/10823 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate having a conductive area, a first pattern formed on the substrate and having a contact hole through which the conductive area is exposed, and a contact plug in the contact hole. The contact plug includes first and second silicon layers. The first silicon layer, formed from a first compound including at least two silicon atoms, is formed in the contact hole to contact a top surface of the conductive area and a side wall of the first pattern. The second silicon layer, formed from a second compound including a number of silicon atoms less than the number of the silicon atoms of the first compound, is formed on the first silicon layer and fills a remaining space of the contact hole, the second silicon layer being spaced apart from the first pattern at an entrance of the contact hole.

Abstract translation: 半导体器件包括具有导电区域的基板，形成在基板上的第一图案，具有导电区域露出的接触孔和接触孔中的接触插塞。 接触插塞包括第一和第二硅层。 在包括至少两个硅原子的第一化合物形成的第一硅层形成在接触孔中以接触导电区域的顶表面和第一图案的侧壁。 在第一硅层上形成由第二化合物构成的第二硅层，该第二化合物包含少于第一化合物的硅原子数的硅原子数，并填充接触孔的剩余空间，第二硅层 在接触孔的入口处与第一图案间隔开。