公开(公告)号：US20140256316A1

公开(公告)日：2014-09-11

申请号：US14204954

申请日：2014-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyun Lee ,  Su-Young Park

IPC: H04W48/16

CPC classification number: H04W48/16 ,  H04W48/18

Abstract: A method and an electronic device for network search. The network search method in an electronic device includes scanning a frequency band corresponding to a first communication system to search for a first Public Land Mobile Network (PLMN); when discovering a second PLMN as a result of the scanning, determining whether a frequency band of the second PLMN and a frequency band of a second communication system overlap each other; and when the frequency band of the second PLMN and the frequency band of the second communication system overlap each other, scanning the other frequency band excluding the overlapping frequency band in the entire frequency band corresponding to the second communication system to search for the first PLMN.

Abstract translation: 一种用于网络搜索的方法和电子设备。 电子设备中的网络搜索方法包括扫描与第一通信系统相对应的频带，以搜索第一公共陆地移动网络（PLMN）; 当作为扫描的结果发现第二PLMN时，确定第二PLMN的频带和第二通信系统的频带是否彼此重叠; 并且当第二PLMN的频带和第二通信系统的频带彼此重叠时，扫描除了与第二通信系统相对应的整个频带中的重叠频带之外的另一频带以搜索第一PLMN。

公开(公告)号：US20210242126A1

公开(公告)日：2021-08-05

申请号：US17235425

申请日：2021-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwi-Chan Jun ,  Seul-Ki Hong ,  Hyun-Soo Kim ,  Sang-Hyun Lee

IPC: H01L23/528 ,  H01L29/423 ,  H01L29/417 ,  H01L27/088

Abstract: A semiconductor device may include a plurality of active patterns and a plurality of gate structure on a substrate, a first insulating interlayer covering the active patterns and the gate structures, a plurality of first contact plugs extending through the first insulating interlayer, a plurality of second contact plugs extending through the first insulating interlayer, and a first connecting pattern directly contacting a sidewall of at least one contact plug selected from the first and second contact plugs. Each of gate structures may include a gate insulation layer, a gate electrode and a capping pattern. Each of first contact plugs may contact the active patterns adjacent to the gate structure. Each of the second contact plugs may contact the gate electrode in the gate structures. An upper surface of the first connecting pattern may be substantially coplanar with upper surfaces of the first and second contact plugs.

公开(公告)号：US20190333915A1

公开(公告)日：2019-10-31

申请号：US16360191

申请日：2019-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-Keun Lee ,  Jong-Chul Park ,  Sang-Hyun Lee

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a first etch stop layer, a second etch stop layer, and an interlayer insulation layer that are stacked on the gate structure, and a contact plug penetrating the interlayer insulation layer, the second etch stop layer, and the first etch stop layer and contacting a sidewall of the gate structure. The contact plug includes a lower portion having a first width and an upper portion having a second width. A lower surface of the contact plug has a stepped shape.

公开(公告)号：USD850497S1

公开(公告)日：2019-06-04

申请号：US29633230

申请日：2018-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Designer： Ki-Soo Kim ,  Seok-Woo Kim ,  Young-Min Park ,  Cheol-Woong Seo ,  Ki-Sang Yoon ,  Se-Lim Yoon ,  Sang-Hyun Lee ,  Sun-Min Lee ,  Seon-Ju Lee ,  Jun-Kyo Lee

公开(公告)号：US10056375B2

公开(公告)日：2018-08-21

申请号：US15687929

申请日：2017-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Young Lee ,  Sang-Hyun Lee ,  Myung-Hoon Jung ,  Do-Hyoung Kim

IPC: H01L21/00 ,  H01L27/088 ,  H01L21/768 ,  H01L21/28 ,  H01L29/45 ,  H01L29/417 ,  H01L27/02 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/11

CPC classification number: H01L27/088 ,  H01L21/28114 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/78

Abstract: A semiconductor device includes a first gate pattern and a second gate pattern on a substrate, the first gate pattern having a first height and the second gate pattern having a second height, an insulating pattern on the substrate covering the first and second gate patterns, the insulating pattern including a trench exposing the substrate between the first and second gate patterns, a spacer contacting at least a portion of a sidewall of the insulating pattern within the trench, the spacer spaced apart from the first and second gate patterns and having a third height larger than the first and second heights, and a contact structure filling the trench.

公开(公告)号：US09930715B2

公开(公告)日：2018-03-27

申请号：US15401564

申请日：2017-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo-Kwang Lee ,  Yeon-Jung Kim ,  Sang-Hyun Lee ,  Jae-Bong Chun ,  Sang-Bum Han ,  Kyung-Tak Hur

IPC: H04W68/00 ,  H04W76/02 ,  H04B1/3827 ,  H04W4/10 ,  H04W4/00 ,  H04W88/04 ,  H04W84/04

CPC classification number: H04W76/15 ,  H04B1/385 ,  H04M1/7253 ,  H04M1/72597 ,  H04W4/10 ,  H04W4/80 ,  H04W8/245 ,  H04W68/005 ,  H04W84/042 ,  H04W88/04

Abstract: An electronic device comprising: a communication interface; a memory; and at least one processor coupled to the memory and the communication interface, wherein the at least one processor is configured to: detect a change of state of the electronic device; transmit to a secondary electronic device a first information item associated with the change of state of the electronic device; receive a second information item from the secondary electronic device in response to the first information item; and perform an operation based on the secondary information item.

公开(公告)号：US20130344666A1

公开(公告)日：2013-12-26

申请号：US13902202

申请日：2013-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon-Seok Moon ,  Jae-Rok Kahng ,  Hyun-Seung Song ,  Dong-Soo Woo ,  Sang-Hyun Lee ,  Hyun-Jung Lee

IPC: H01L29/788

CPC classification number: H01L29/788 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

Abstract: Methods of fabricating semiconductor device are provided including forming first through third silicon crystalline layers on first through third surfaces of an active region; removing the first silicon crystalline layer to expose the first surface; forming a bit line stack on the exposed first surface; forming bit line sidewall spacers on both side surfaces of the bit line stack to be vertically aligned with portions of the second and third silicon crystalline layers of the active region; removing the second and third silicon crystalline layers disposed under the bit line sidewall spacers to expose the second and third surfaces of the active region; and forming storage contact plugs in contact with the second and third surfaces of the active region.

Abstract translation: 提供制造半导体器件的方法包括在有源区的第一至​​第三表面上形成第一至第三硅结晶层; 去除所述第一硅晶层以暴露所述第一表面; 在暴露的第一表面上形成位线堆叠; 在所述位线堆叠的两个侧表面上形成位线侧壁间隔物以与所述有源区域的所述第二和第三硅结晶层的部分垂直对准; 去除设置在位线侧壁间隔物下方的第二和第三硅结晶层，以暴露有源区的第二和第三表面; 以及形成与所述有源区域的第二和第三表面接触的存储接触插塞。

公开(公告)号：US11616016B2

公开(公告)日：2023-03-28

申请号：US17235425

申请日：2021-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwi-Chan Jun ,  Seul-Ki Hong ,  Hyun-Soo Kim ,  Sang-Hyun Lee

IPC: H01L23/528 ,  H01L29/423 ,  H01L29/417 ,  H01L27/088

Abstract: A semiconductor device may include a plurality of active patterns and a plurality of gate structure on a substrate, a first insulating interlayer covering the active patterns and the gate structures, a plurality of first contact plugs extending through the first insulating interlayer, a plurality of second contact plugs extending through the first insulating interlayer, and a first connecting pattern directly contacting a sidewall of at least one contact plug selected from the first and second contact plugs. Each of gate structures may include a gate insulation layer, a gate electrode and a capping pattern. Each of first contact plugs may contact the active patterns adjacent to the gate structure. Each of the second contact plugs may contact the gate electrode in the gate structures. An upper surface of the first connecting pattern may be substantially coplanar with upper surfaces of the first and second contact plugs.

公开(公告)号：US10991620B2

公开(公告)日：2021-04-27

申请号：US16282441

申请日：2019-02-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hyun Lee ,  Sung-Woo Kang ,  Keun-Hee Bai ,  Hak-Yoon Ahn ,  Seong-Han Oh ,  Young-Mook Oh

IPC: H01L21/768 ,  H01L27/11 ,  H01L27/088 ,  H01L23/535 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8234

Abstract: A semiconductor device includes gates extending in a first direction on a substrate, each gate of the gates including a gate insulation layer, a gate electrode, and a first spacer, first contact plugs contacting the substrate between adjacent ones of the gates, the first contact plugs being spaced apart from sidewalls of corresponding ones of the gates, a second contact plug contacting an upper surface of a corresponding gate electrode, the second contact plug being between first contact plugs, and an insulation spacer in a gap between the second contact plug and an adjacent first contact plug, the insulation spacer contacting sidewalls of the second contact plug and the adjacent first contact plug, and upper surfaces of the second contact plug and the adjacent first contact plug being substantially coplanar with each other.

公开(公告)号：US10050114B2

公开(公告)日：2018-08-14

申请号：US15652396

申请日：2017-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bok-Young Lee ,  Sung-Woo Kang ,  Sang-Hyun Lee ,  Hak-Yoon Ahn ,  Young-Mook Oh ,  In-Keun Lee ,  Seong-Han Oh ,  Young-Hun Choi

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/45 ,  H01L21/8234 ,  H01L23/535 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/41791 ,  H01L21/76808 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/535 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes an active region in a shape of a fin extending in a first direction, the fin having source/drain regions spaced apart therein, gate structures crossing the fin between the source/drain regions, each including a gate electrode, a first contact structure in electrical contact with a first source/drain region, the first contact structure including a first lower contact and a first upper contact directly thereon, a second contact structure in electrical contact with a gate electrode of a gate structure, the second contact structure including a second lower contact and a second upper contact directly thereon, and a third contact structure in electrical contact with a gate electrode of a second gate structure and in electrical contact with a second source drain region, the third contact structure including a third lower contact and a third upper contact directly thereon.