公开(公告)号：US10056928B2

公开(公告)日：2018-08-21

申请号：US14825017

申请日：2015-08-12

Applicant: Samsung Electronics Co., Ltd. ,  Korea Advanced Institute of Science and Technology

Inventor： Myung-Gil Kang ,  Wan Choi ,  Dae-Kyu Shin ,  Sang-Wook Suh

IPC: H04B1/04 ,  H04B1/12

CPC classification number: H04B1/126

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-Generation (4G) communication system such as a Long Term Evolution (LTE). A method for controlling interference in a signal transmitting apparatus in a mobile communication system is provided. The method includes transmitting data to a first signal receiving apparatus using a plurality of channels; receiving information indicating whether at least one of the plurality of channels exists as an interference channel in a second signal receiving apparatus from the second signal receiving apparatus; receiving interference control information for controlling interference for the second signal receiving apparatus from the second signal receiving apparatus based on the received information, and generating interference control data based on the interference control information; and transmitting the interference control data to the first signal receiving apparatus.

公开(公告)号：US09966376B2

公开(公告)日：2018-05-08

申请号：US15231134

申请日：2016-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mun-Hyeon Kim ,  Chang-Woo Noh ,  Keun-Hwi Cho ,  Myung-Gil Kang ,  Shigenobu Maeda

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238 ,  H01L27/02

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51

Abstract: Disclosed are CMOS device and CMOS inverter. The CMOS device includes a substrate having active lines extending in a first direction and defined by a device isolation layer, the substrate being divided into an NMOS area, a PMOS area and a boundary area interposed between the NMOS and the PMOS areas and having the device isolation layer without the active line, a gate line extending in a second direction across the active lines and having a first gate structure on the active line in the first area, a second gate structure on the active line in the second and a third gate structure on the device isolation layer in the third area. The electrical resistance and parasitic capacitance of the third gate structure are smaller than those of the NMOS and the PMOS gate structures. Accordingly, better AC and DC performance of the CMOS device can be obtained.

公开(公告)号：US11469237B2

公开(公告)日：2022-10-11

申请号：US16388347

申请日：2019-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum Kim ,  Myung-Gil Kang ,  Kang-Hun Moon ,  Cho-Eun Lee ,  Su-Jin Jung ,  Min-Hee Choi ,  Yang Xu ,  Dong-Suk Shin ,  Kwan-Heum Lee ,  Hoi-Sung Chung

IPC: H01L27/088 ,  H01L27/11 ,  H01L29/66 ,  H01L29/78 ,  H01L23/485 ,  H01L21/8234 ,  H01L29/417 ,  H01L23/528 ,  H01L29/08 ,  H01L29/161 ,  H01L29/45 ,  H01L27/092 ,  H01L29/165

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

公开(公告)号：US20190244963A1

公开(公告)日：2019-08-08

申请号：US16388347

申请日：2019-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum Kim ,  Myung-Gil Kang ,  Kang-Hun Moon ,  Cho-Eun Lee ,  Su-Jin Jung ,  Min-Hee Choi ,  Yang Xu ,  Dong-Suk Shin ,  Kwan-Heum Lee ,  Hoi-Sung Chung

IPC: H01L27/11 ,  H01L29/66 ,  H01L29/161 ,  H01L29/78 ,  H01L29/08 ,  H01L23/528 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  H01L23/485 ,  H01L29/45

CPC classification number: H01L27/1104 ,  H01L21/823431 ,  H01L23/485 ,  H01L23/5283 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

公开(公告)号：US09673099B2

公开(公告)日：2017-06-06

申请号：US15136450

申请日：2016-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung-Gil Kang ,  Sung-Bong Kim ,  Chang-Woo Oh ,  Dong-Won Kim

IPC: H01L21/8234 ,  H01L29/775 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/823431 ,  H01L21/823418 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

Abstract: An integrated circuit device includes a first transistor having a first channel between a first source/drain, and a second transistor having a second channel between a second source/drain. The first transistor operates based on a first amount of current and the second transistor operates based on a second amount of current different from the first amount of current. The first and second channels have fixed channel widths. The fixed channel widths may be based on fins or nanowires included in the first and second transistors.

公开(公告)号：US20170047966A1

公开(公告)日：2017-02-16

申请号：US15235066

申请日：2016-08-11

Applicant: Samsung Electronics Co., Ltd ,  Korea Advanced Institute of Science & Technology

Inventor： Kwang-Taik Kim ,  Wan Choi ,  Myung-Gil Kang ,  Hyo-Woon Seo ,  Kyung-Rak Son

IPC: H04B3/20 ,  H04W72/02 ,  H04L27/34 ,  H04B7/06 ,  H04W4/00 ,  H04W72/04 ,  H04B7/04

Abstract: A method includes generating preference information according to each of a plurality of base stations including at least one adjacent base station and transmitting the generated preference information to a serving base station, receiving, from the serving base station, information related to beams of the serving base station and the at least one adjacent base station determined based on the preference information, and receiving a signal by using the information related to the beams, wherein the information related to the beams includes beam information on a partial area in which interference signals transmitted by the at least one adjacent base station are aligned among a whole reception area of the terminal. A serving base station includes a controller configured to configure beams for a partial area in which interference signals transmitted by the at least one adjacent base station are aligned among a whole reception area of the terminal

Abstract translation: 一种方法包括根据包括至少一个相邻基站的多个基站中的每一个生成偏好信息，并将所生成的偏好信息发送到服务基站，从服务基站接收与服务基站的波束相关的信息 以及基于偏好信息确定的至少一个相邻基站，并且通过使用与该波束相关的信息来接收信号，其中与波束相关的信息包括关于部分区域的波束信息，其中由 至少一个相邻基站在终端的整个接收区域之间对齐。 服务基站包括：控制器，被配置为对由所述至少一个相邻基站发送的干扰信号在所述终端的整个接收区域中对齐的部分区域配置波束

公开(公告)号：US09324850B2

公开(公告)日：2016-04-26

申请号：US14162052

申请日：2014-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung-Gil Kang ,  Sung-Bong Kim ,  Chang-Woo Oh ,  Dong-Won Kim

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/823431 ,  H01L21/823418 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

Abstract: An integrated circuit device includes a first transistor having a first channel between a first source/drain, and a second transistor having a second channel between a second source/drain. The first transistor operates based on a first amount of current and the second transistor operates based on a second amount of current different from the first amount of current. The first and second channels have fixed channel widths. The fixed channel widths may be based on fins or nanowires included in the first and second transistors.

Abstract translation: 集成电路器件包括第一晶体管，其具有在第一源极/漏极之间的第一沟道和在第二源极/漏极之间具有第二沟道的第二晶体管。 第一晶体管基于第一电流量而工作，并且第二晶体管基于不同于第一电流量的第二电流量来操作。 第一和第二通道具有固定的通道宽度。 固定通道宽度可以基于包括在第一和第二晶体管中的翅片或纳米线。