公开(公告)号：US20230317607A1

公开(公告)日：2023-10-05

申请号：US18080402

申请日：2022-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungtae SUNG ,  Yunsun JANG ,  Moorym CHOI

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/492 ,  H01L29/08 ,  H10B41/41 ,  H10B43/35 ,  H01L23/522 ,  H01L23/00 ,  H10B43/40 ,  H01L29/10 ,  H10B41/35 ,  H01L29/423

CPC classification number: H01L23/5283 ,  H01L23/492 ,  H01L23/5226 ,  H01L23/53209 ,  H01L24/08 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42328 ,  H01L29/42344 ,  H01L23/49816 ,  H01L2224/08146 ,  H01L2924/1431 ,  H01L2924/1438

Abstract: A semiconductor device includes a first semiconductor structure including a lower bonding structure, and a second semiconductor structure including a second substrate disposed on the first semiconductor structure, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to a lower surface of the second substrate, an upper bonding structure bonded to the lower bonding structure, a plate conductive layer disposed on an upper surface of the second substrate, electrically connected to a channel layer, and including a metal material, and an isolation structure penetrating an entirety of the gate electrodes and extending in a second direction perpendicular to the first direction. The isolation structure includes a vertical conductive layer that extends from and is integrated with the plate conductive layer, and that includes a same metal material as the metal material of the plate conductive layer.

公开(公告)号：US20220320025A1

公开(公告)日：2022-10-06

申请号：US17529462

申请日：2021-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym CHOI ,  Jiyoung KIM ,  Sanghee YOON

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L27/11556 ,  H01L27/11582

Abstract: A three-dimensional semiconductor memory device may include a first substrate including a cell array region and a cell array contact region, a peripheral circuit structure on the first substrate, and a cell array structure. The cell array structure may include a stack on the peripheral circuit structure, first vertical channel structures and second vertical channel structures on the cell array region and penetrating the stack, and a second substrate connected to the first vertical channel structures and second vertical channel structures. The stack may be between the peripheral circuit structure and the second substrate. The second substrate may include a first portion and a second portion. The first portion may contact the first vertical channel structures and may be doped a first conductivity type. The second portion may contact the second vertical channel structures and may be doped a second conductivity type different from the first conductivity type.

公开(公告)号：US20190341456A1

公开(公告)日：2019-11-07

申请号：US16515412

申请日：2019-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moorym CHOI ,  Bongyong LEE ,  Junhee LIM

IPC: H01L29/10 ,  H01L29/78 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A three-dimensional semiconductor memory device includes common source regions, an electrode structure between the common source regions, first channel structures penetrating the electrode structure, and second channel structures between the first channel structures and penetrating the electrode structures. The electrode structure includes electrodes vertically stacked on a substrate. The first channel structures include a first semiconductor pattern and a first vertical insulation layer. The second channel structures include a second vertical insulation layer surrounding a second semiconductor pattern. The second vertical insulation layer has a bottom surface lower than a bottom surface of the first vertical insulation layer.

公开(公告)号：US20190139980A1

公开(公告)日：2019-05-09

申请号：US16036000

申请日：2018-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taeyoung KIM ,  Moorym CHOI ,  DONGCHAN KIM

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L23/532 ,  G11C16/04 ,  G11C16/34

Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of detecting electrical failure thereof. The three-dimensional semiconductor memory device includes a substrate with a first conductivity including a cell array region and an extension region having different threshold voltages from each other, a stack structure on the substrate and including stacked electrodes, an electrical vertical channel penetrating the stack structure on the cell array region, and a dummy vertical channel penetrating the stack structure on the extension region. The substrate comprises a pocket well having the first conductivity and provided with the stack structure thereon, and a deep well surrounding the pocket well and having a second conductivity opposite to the first conductivity.

公开(公告)号：US20240341100A1

公开(公告)日：2024-10-10

申请号：US18386429

申请日：2023-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jimin LEE ,  Jungtae SUNG ,  Sunil SHIM ,  Yunsun JANG ,  Wonseok CHO ,  Moorym CHOI ,  Chulmin CHOI

IPC: H10B43/50 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/50 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes gate electrode structures, a first division pattern, a second division pattern, and a memory channel structure. Each gate electrode structure includes gate electrodes spaced apart from each other on a substrate in a first direction substantially perpendicular to an upper surface of the substrate. Each gate electrode extends in a second direction substantially parallel to the upper surface of the substrate. The gate electrode structures are spaced apart from each other in a third direction substantially parallel to the upper surface and crossing the second direction. The first division pattern extends in the second direction between the gate electrode structures on the substrate. The second division pattern extends in the third direction on the substrate, and is on sidewalls of end portions in the second direction of the gate electrode structures. The memory channel structure extends in the first direction through each gate electrode structure.

公开(公告)号：US20240057333A1

公开(公告)日：2024-02-15

申请号：US18134344

申请日：2023-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moorym CHOI ,  Jungtae SUNG ,  Sunil SHIM ,  Yunsun JANG

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor memory device includes: a stack including interlayer insulating layers and conductive patterns, which are alternately stacked; a source conductive pattern on the stack; and vertical structures provided to penetrate the stack and connected to the source conductive pattern. Each of the vertical structures includes: a vertical channel pattern; a data storage pattern enclosing an outer side surface of the vertical channel pattern; a vertical insulating pillar in the vertical channel pattern; and a vertical conductive pillar disposed between the vertical insulating pillar and the source conductive pattern to connect the vertical channel pattern to the source conductive pattern.

公开(公告)号：US20240040791A1

公开(公告)日：2024-02-01

申请号：US18186531

申请日：2023-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moorym CHOI ,  Jungtae SUNG ,  Sunil SHIM ,  Yunsun JANG

IPC: H10B43/40 ,  H10B43/10 ,  H01L23/528 ,  H10B43/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/35 ,  H10B41/27 ,  H10B41/40

CPC classification number: H10B43/40 ,  H10B43/10 ,  H01L23/5283 ,  H10B43/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/35 ,  H10B41/27 ,  H10B41/40

Abstract: A three-dimensional semiconductor memory device is provided. The memory device includes a substrate, a peripheral circuit structure on the substrate, and a cell array structure on the peripheral circuit structure and including a cell array region and a cell array contact region. The cell array structure includes a stack structure including alternately stacked interlayer insulating layers and gate electrodes, a first source conductive pattern, a second source conductive pattern, and a third source conductive pattern sequentially stacked on the stack structure. The first to third source conductive patterns include different materials from each other. Vertical channel structures extending into a lower portion of the first source conductive pattern through the stack structure is included. The first to third source conductive patterns extend from the cell array region to the cell array contact region. The vertical channel structures include vertical semiconductor patterns that contact to the first source conductive pattern.

公开(公告)号：US20230275054A1

公开(公告)日：2023-08-31

申请号：US18086086

申请日：2022-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YUNSUN JANG ,  Moorym CHOI

IPC: H01L23/00 ,  H10B41/27 ,  H10B43/27 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L27/11556 ,  H01L27/11582 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor device includes a first substrate structure including a substrate, circuit elements, and first bonding metal layers, and a second substrate structure directly on the first substrate structure. The second substrate structure includes a plate layer comprising a conductive material, gate electrodes stacked below the plate layer, channel structures passing through the gate electrodes and each including a channel layer, separation regions penetrating through the gate electrodes and extending in first and second directions and source contacts in the plate layer and disposed on the separation regions. The source contacts extend in the second direction. Second bonding metal layers are connected to the first bonding metal layers. The plate layer is in direct contact with lateral side surfaces of the source contacts and an upper end of the channel layer of each of the channel structures, and is electrically connected to the source contacts and the channel layer.

公开(公告)号：US20230021449A1

公开(公告)日：2023-01-26

申请号：US17702137

申请日：2022-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym CHOI ,  Jungtae SUNG

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor device includes: circuit devices on a first substrate; a lower interconnection structure electrically connected to the circuit devices; a lower bonding structure connected to the lower interconnection structure; an upper bonding structure on the lower bonding structure; an upper interconnection structure connected to the upper bonding structure; a second substrate on the upper interconnection structure; gate electrodes between the upper interconnection structure and the second substrate; channel structures penetrating the gate electrodes and each including a channel layer; via patterns on the second substrate; a source contact plug spaced apart from the second substrate on an external side of the second substrate and having an upper surface higher than the second substrate and a lower surface lower than a lowermost gate electrode; and a source connection pattern contacting upper surfaces of each of the via patterns and the upper surface of the source contact plug.