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    NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM COMPRISING THE SAME
    1.
    发明申请
    NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM COMPRISING THE SAME 有权

    公开(公告)号：US20220173119A1

    公开(公告)日：2022-06-02

    申请号：US17368029

    申请日：2021-07-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Moorym CHOI ,  Jungtae SUNG ,  Sanghee YOON ,  Wooyong JEON ,  Junyoung CHOI ,  Yoonjo HWANG

    IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/108

    Abstract: A nonvolatile memory device includes a first structure and a second structure bonded to the first structure. The second structure includes a low-resistance conductive layer, a common source line layer on the low-resistance conductive layer, a stack structure above the common source line layer, a plurality of channel structures passing through a cell region of the stack structure and contacting the common source line layer, a dummy channel structure passing through a step region of the stack structure and contacting the common source line layer, a second insulating structure on the stack structure, a plurality of second bonding pads on the second insulating structure, and a second interconnect structure in the second insulating structure.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    2.
    发明公开
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20230320096A1

    公开(公告)日：2023-10-05

    申请号：US18076090

    申请日：2022-12-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Moorym CHOI ,  Jungtae SUNG ,  Yunsun JANG

    IPC: H01L27/11582 ,  H01L27/11573

    CPC classification number: H01L27/11582 ,  H01L27/11573

    Abstract: A three-dimensional semiconductor memory device includes a substrate, a peripheral circuit structure provided on the substrate, and a cell array structure provided on the peripheral circuit structure. The cell array structure includes a stack including alternating interlayer insulating layers and conductive patterns, the conductive patterns including gate electrodes and a first source conductive pattern that is an uppermost pattern of the conductive patterns, a second source conductive pattern provided on the stack and in contact with a top surface of the first source conductive pattern, the second source conductive pattern including a material different from a material of the first source conductive pattern, and vertical channel structures provided to penetrate the stack and to be inserted into a lower portion of the second source conductive pattern. The vertical channel structures include vertical semiconductor patterns connected to the second source conductive pattern.

    SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20220285302A1

    公开(公告)日：2022-09-08

    申请号：US17543250

    申请日：2021-12-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Moorym CHOI ,  Jungtae SUNG ,  Junyoung CHOI

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

    Abstract: A semiconductor device includes a first semiconductor structure including a first substrate, circuit devices on the first substrate, a lower interconnection structure on the circuit devices, and a lower bonding structure electrically connected to the lower interconnection structure, and a second semiconductor structure including a second substrate disposed on the first semiconductor structure, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to a lower surface of the second substrate, channel structures that penetrate the gate electrodes and extend in the first direction, and an upper bonding structure electrically connected to the gate electrodes and the channel structures and bonded to the lower bonding structure. The second semiconductor structure further includes a first via connected to an upper portion of the second substrate, a second via spaced apart from the first via and the second substrate, and a contact plug.

    VERTICAL MEMORY DEVICES INCLUDING DIVISION PATTERNS
    6.
    发明公开
    VERTICAL MEMORY DEVICES INCLUDING DIVISION PATTERNS 审中-公开

    公开(公告)号：US20240341100A1

    公开(公告)日：2024-10-10

    申请号：US18386429

    申请日：2023-11-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jimin LEE ,  Jungtae SUNG ,  Sunil SHIM ,  Yunsun JANG ,  Wonseok CHO ,  Moorym CHOI ,  Chulmin CHOI

    IPC: H10B43/50 ,  H10B43/27 ,  H10B43/40

    CPC classification number: H10B43/50 ,  H10B43/27 ,  H10B43/40

    Abstract: A semiconductor device includes gate electrode structures, a first division pattern, a second division pattern, and a memory channel structure. Each gate electrode structure includes gate electrodes spaced apart from each other on a substrate in a first direction substantially perpendicular to an upper surface of the substrate. Each gate electrode extends in a second direction substantially parallel to the upper surface of the substrate. The gate electrode structures are spaced apart from each other in a third direction substantially parallel to the upper surface and crossing the second direction. The first division pattern extends in the second direction between the gate electrode structures on the substrate. The second division pattern extends in the third direction on the substrate, and is on sidewalls of end portions in the second direction of the gate electrode structures. The memory channel structure extends in the first direction through each gate electrode structure.

    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME
    9.
    发明申请
    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20230021449A1

    公开(公告)日：2023-01-26

    申请号：US17702137

    申请日：2022-03-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Moorym CHOI ,  Jungtae SUNG

    IPC: H01L23/528 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

    Abstract: A semiconductor device includes: circuit devices on a first substrate; a lower interconnection structure electrically connected to the circuit devices; a lower bonding structure connected to the lower interconnection structure; an upper bonding structure on the lower bonding structure; an upper interconnection structure connected to the upper bonding structure; a second substrate on the upper interconnection structure; gate electrodes between the upper interconnection structure and the second substrate; channel structures penetrating the gate electrodes and each including a channel layer; via patterns on the second substrate; a source contact plug spaced apart from the second substrate on an external side of the second substrate and having an upper surface higher than the second substrate and a lower surface lower than a lowermost gate electrode; and a source connection pattern contacting upper surfaces of each of the via patterns and the upper surface of the source contact plug.

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