公开(公告)号：US20240179912A1

公开(公告)日：2024-05-30

申请号：US18436169

申请日：2024-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym CHOI ,  Jungtae SUNG ,  Sanghee YOON ,  Wooyong JEON ,  Junyoung CHOI ,  Yoonjo HWANG

IPC: H10B43/27 ,  H10B12/00 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B12/50 ,  H10B43/40

Abstract: A nonvolatile memory device includes a first structure and a second structure bonded to the first structure. The second structure includes a low-resistance conductive layer, a common source line layer on the low-resistance conductive layer, a stack structure above the common source line layer, a plurality of channel structures passing through a cell region of the stack structure and contacting the common source line layer, a dummy channel structure passing through a step region of the stack structure and contacting the common source line layer, a second insulating structure on the stack structure, a plurality of second bonding pads on the second insulating structure, and a second interconnect structure in the second insulating structure.

公开(公告)号：US20220173119A1

公开(公告)日：2022-06-02

申请号：US17368029

申请日：2021-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym CHOI ,  Jungtae SUNG ,  Sanghee YOON ,  Wooyong JEON ,  Junyoung CHOI ,  Yoonjo HWANG

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/108

Abstract: A nonvolatile memory device includes a first structure and a second structure bonded to the first structure. The second structure includes a low-resistance conductive layer, a common source line layer on the low-resistance conductive layer, a stack structure above the common source line layer, a plurality of channel structures passing through a cell region of the stack structure and contacting the common source line layer, a dummy channel structure passing through a step region of the stack structure and contacting the common source line layer, a second insulating structure on the stack structure, a plurality of second bonding pads on the second insulating structure, and a second interconnect structure in the second insulating structure.

公开(公告)号：US20230083114A1

公开(公告)日：2023-03-16

申请号：US17828960

申请日：2022-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonjo HWANG ,  Jiyoung KIM

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor device includes a first substrate structure including a substrate, circuit devices, and first bonding metal layers on the circuit devices, and a second substrate structure connected to the first substrate structure on the first substrate structure, wherein the second substrate structure includes a plate layer having a first region and a second region, gate electrodes stacked below the plate layer and extending by different lengths in a second direction in the second region, channel structures penetrating the gate electrodes and each including a channel layer, in the first region, input/output contact structures penetrating the plate layer and the gate electrodes and each including a contact conductive layer, in the second region, and second bonding metal layers connected to the first bonding metal layers, wherein a level of upper surfaces of the input/output contact structures is higher than a level of upper surfaces of the channel structures.

公开(公告)号：US20220375888A1

公开(公告)日：2022-11-24

申请号：US17545117

申请日：2021-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moorym CHOI ,  Yoonjo HWANG

IPC: H01L23/00 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/065 ,  H01L25/18

Abstract: A three-dimensional semiconductor memory device includes a first substrate, a peripheral circuit structure on the first substrate, a cell array structure on the peripheral circuit structure, the cell array structure including a stack structure having alternating interlayer dielectric layers and gate electrodes, a first insulating layer covering the stack structure, and a second substrate on the stack structure and the first insulating layer, the stack structure being between a bottom surface of the second substrate and the peripheral circuit structure, a second insulating layer on the cell array structure, a first penetration contact penetrating the first insulating layer, the second substrate, and the second insulating layer, and a second penetration contact penetrating the first insulating layer and the second insulating layer, the second penetration contact being spaced apart from the second substrate, and the first and second penetration contacts having widths decreasing with increasing distance from the first substrate.