公开(公告)号：US20240203875A1

公开(公告)日：2024-06-20

申请号：US18239504

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiwon KIM ,  Jiyoung KIM ,  Woosung YANG ,  Sukkang SUNG

IPC: H01L23/528 ,  G11C16/04 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H01L23/5283 ,  G11C16/0483 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor device including a first semiconductor structure overlapping a second semiconductor structure, the second semiconductor structure having first and second regions and including a plate layer; gate electrodes spaced apart from each other in a first direction; channel structures passing through the gate electrodes; gate separation regions extending in a second direction; first and second upper isolation regions dividing an upper gate electrode into first, second and third sub-gate electrodes between adjacent gate separation regions; and contact plugs extending in the first direction, each of the first and second upper isolation regions has a region extending in a third direction, and the first sub-gate electrode has a first pad region having a first width and a second pad region having a second width narrower than the first width in a fourth direction, and the first sub-gate electrode is connected to one of the contact plugs.

公开(公告)号：US20240114704A1

公开(公告)日：2024-04-04

申请号：US18187803

申请日：2023-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonyoung KWON ,  Jiyoung KIM ,  Woosung YANG ,  Sukkang SUNG

IPC: H10B80/00 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B80/00 ,  H10B43/27 ,  H10B43/40

Abstract: A three-dimensional semiconductor memory device may include a first substrate, a peripheral circuit structure on the first substrate, the peripheral circuit structure including first bonding pads in an upper portion of the peripheral circuit structure, and a cell array structure on the peripheral circuit structure. The cell array structure may include a second substrate, a stack interposed between the peripheral circuit structure and the second substrate, a first insulating layer enclosing the stack, a dummy plug penetrating the first insulating layer, a second insulating layer on the dummy plug, and second bonding pads interposed between the stack and the peripheral circuit structure and connected to the dummy plug. The first bonding pads may contact the second bonding pads, and the dummy plug may be electrically connected to the first bonding pads and the second bonding pads. A top surface of the dummy plug may contact the second insulating layer.

公开(公告)号：US20210035991A1

公开(公告)日：2021-02-04

申请号：US16827778

申请日：2020-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihye KIM ,  Jaehoon LEE ,  Jiyoung KIM ,  Bongtae PARK ,  Jaejoo SHIM

IPC: H01L27/112 ,  H01L27/32 ,  H01L27/11585

Abstract: A semiconductor device includes a substrate having a conductive region and an insulating region; gate electrodes including sub-gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate and extending in a second direction perpendicular to the first direction and gate connectors connecting the sub-gate electrodes disposed on the same level; channel structures penetrating through the gate electrodes and extending in the conductive region of the substrate; and a first dummy channel structure penetrating through the gate electrodes and extending in the insulating region of the substrate and disposed adjacent to at least one side of the gate connectors in a third direction perpendicular to the first and second directions.

公开(公告)号：US20190103407A1

公开(公告)日：2019-04-04

申请号：US16038052

申请日：2018-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung KIM ,  Kiseok LEE ,  Bong-Soo KIM ,  Junsoo KIM ,  Dongsoo WOO ,  Kyupil LEE ,  HyeongSun HONG ,  Yoosang HWANG

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/0688 ,  H01L27/1085 ,  H01L28/86

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

公开(公告)号：US20240405091A1

公开(公告)日：2024-12-05

申请号：US18541229

申请日：2023-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNHYOUNG KIM ,  Joonyoung KWON ,  Jiyoung KIM ,  Sukkang SUNG

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/768

Abstract: A semiconductor device includes a gate stacking structure including alternating gate electrodes and insulation layers on an insulation portion, a channel structure crossing the insulation portion and extending through the gate stacking structure, and a horizontal conductive layer connected to the channel structure between the insulation portion and the gate stacking structure, the horizontal conductive layer including a doped monocrystalline semiconductor layer having a dopant.

公开(公告)号：US20240178168A1

公开(公告)日：2024-05-30

申请号：US18237962

申请日：2023-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho KIM ,  Woosung YANG ,  Joonyoung KWON ,  Jiyoung KIM ,  Sukkang SUNG

IPC: H01L23/00 ,  H10B41/50 ,  H10B43/50

CPC classification number: H01L24/08 ,  H10B41/50 ,  H10B43/50 ,  H01L2224/08145

Abstract: A semiconductor device includes a first substrate structure including a substrate, circuit elements on the substrate, a first interconnection structure on the circuit elements, and first metal bonding layers on the first interconnection structure; and a second substrate structure connected to the first substrate structure, and the second substrate structure includes: a plating layer; gate electrodes stacked and spaced apart from each other in a first direction below the plating layer; channel structures penetrating through the gate electrodes and extending in the first direction; a separation region penetrating through the gate electrodes and extending in a second direction; a second interconnection structure below the gate electrodes and the channel structures; second metal bonding layers below the second interconnection structure and connected to the first metal bonding layers; and dummy pattern layers between the second metal bonding layers, extending in the second direction, and including an insulating material.

公开(公告)号：US20230378083A1

公开(公告)日：2023-11-23

申请号：US18172534

申请日：2023-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahreum LEE ,  Jimo GU ,  Jiyoung KIM ,  Sukkang SUNG

IPC: H01L23/544 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC classification number: H01L23/544 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H01L2223/54426

Abstract: A semiconductor device may include an align key on a plate layer. The align key may include a first align layer connected to a second align layer. The first align layer may have a first length in a first direction, a second length in a second direction, and an air gap in the first align layer. The second align layer may be on the first align layer and may have a third length. The first direction may be perpendicular to an upper surface of the plate layer. The second length may be smaller than the first length. The third length may be smaller than the second length in the second direction.

公开(公告)号：US20230187971A1

公开(公告)日：2023-06-15

申请号：US18105532

申请日：2023-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghee AN ,  Sangwon KIM ,  Jiyoung KIM ,  Taekeun KIM ,  Chankyu LIM ,  Jiwoo LEE

IPC: H02J50/10 ,  H02J7/00 ,  G06F3/0354 ,  G06F3/038

CPC classification number: H02J50/10 ,  H02J7/0044 ,  G06F3/03545 ,  G06F3/038

Abstract: Various embodiments disclosed in the present document relate to an electronic device capable of wirelessly charging a pen input device. According to various embodiments disclosed in the present document, provided is an electronic device comprising: a housing that accommodates an electronic component in the inner space thereof; a wireless charging coil disposed on the inner surface of the housing forming the inner space; a first magnetic body group disposed on the inner surface of the housing and aligned with the wireless charging coil in a first direction; and a magnetic field sensor, disposed to be spaced apart from the first magnetic body group by a predetermined distance, for recognizing reverse attachment of a pen input device attachable to the electronic device. Various other embodiments may be provided.

公开(公告)号：US20220115382A1

公开(公告)日：2022-04-14

申请号：US17555829

申请日：2021-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjun LEE ,  Sang Chul SHIN ,  Bong-Soo KIM ,  Jiyoung KIM

IPC: H01L27/108 ,  G11C5/06 ,  H01L21/768 ,  H01L23/528

Abstract: A semiconductor memory device may include a substrate, a bit line structure extending in one direction on the substrate, the bit line structure including a sidewall, a storage node contact on the sidewall of the bit line structure, first and second spacers between the sidewall of the bit line structure and the storage node contact, the first spacer separated from the second spacer by a space between the first spacer and the second spacer, an interlayer dielectric layer on the bit line structure, the interlayer dielectric layer including a bottom surface, a spacer capping pattern extending downward from the bottom surface of the interlayer dielectric layer toward the space between the first and second spacers, and a landing pad structure penetrating the interlayer dielectric layer, the landing pad structure coupled to the storage node contact.

公开(公告)号：US20200152654A1

公开(公告)日：2020-05-14

申请号：US16514557

申请日：2019-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min HWANG ,  Joon-Sung LIM ,  Jiyoung KIM ,  Jiwon KIM ,  Woosung YANG

IPC: H01L27/11578 ,  H01L27/11573 ,  H01L27/11568 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11551

Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. A three-dimensional semiconductor memory device including a substrate including a cell array region and a connection region, an electrode structure including a plurality of electrodes and a plurality of dielectric layers alternately stacked on the substrate, the electrode structure having a stepwise portion on the connection region, an etch stop structure on the stepwise portion of the electrode structure, and a plurality of contact plugs on the connection region, the contact plugs penetrating the etch stop structure and connected to corresponding pad portions of the electrodes, respectively, may be provided. The etch stop structure may include an etch stop pattern and a horizontal dielectric layer, which has have a uniform thickness and covers a top surface and a bottom surface of an etch stop pattern.