公开(公告)号：US09972527B2

公开(公告)日：2018-05-15

申请号：US15263822

申请日：2016-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Eun Kim ,  Yong-Kwan Kim ,  Se-Myeong Jang ,  Yoo-Sang Hwang ,  Bong-Soo Kim

IPC: H01L21/00 ,  H01L21/768 ,  G11C11/408 ,  G11C11/4091 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/108 ,  G11C11/406

CPC classification number: H01L21/7682 ,  G11C11/40615 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4091 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/10885 ,  H01L28/00

Abstract: A semiconductor device includes a substrate including a plurality of active areas. A conductive pattern is in contact with an active area. First and second conductive line structures face first and second side walls of the conductive pattern. An air spacer is disposed between the first and second side walls. The first and second conductive line structures include a conductive line and a conductive line mask layer. The conductive line mask layer includes a lower portion having a first width and an upper portion having a second width narrower than the first width. The air spacer includes a first air spacer disposed on a side wall of the lower portion of the conductive line mask layer and a second air spacer disposed on a side wall of the upper portion of the conductive line mask layer. The second air spacer is connected with the first air spacer.

公开(公告)号：US09847278B2

公开(公告)日：2017-12-19

申请号：US15095327

申请日：2016-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Kim ,  Yongkwan Kim ,  Semyeong Jang ,  Jaehyoung Choi ,  Yoosang Hwang ,  Bong-Soo Kim

IPC: H01L21/70 ,  H01L21/76 ,  H01L23/482 ,  H01L29/06 ,  H01L21/762 ,  H01L21/768 ,  H01L27/108 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/4821 ,  H01L21/76264 ,  H01L21/7682 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L29/0649

Abstract: A semiconductor device includes first and second bit line structures on a substrate and spaced apart from each other, a via plug partially filling between the first and second bit line structures, a via pad in contact with an upper surface of the via plug and an upper sidewall of the first bit line structure, the via pad being spaced apart from an upper portion of the second bit line structure, a first cavity filled with air being between the via plug and the first bit line structure and a second cavity filled with air between the via plug and the second bit line structure, A gap capping spacer having a first portion on the upper sidewall of the first bit line structure and a second portion covers the first air spacer. A horizontal width of the first portion is smaller than that of the second portion.

公开(公告)号：US20170236894A1

公开(公告)日：2017-08-17

申请号：US15383159

申请日：2016-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Kim ,  Ki-hyung NAM ,  Byung Yoon KIM ,  Bong-Soo KIM ,  Eunjung KIM ,  Yoosang HWANG

IPC: H01L49/02

CPC classification number: H01L28/56 ,  H01L27/10808 ,  H01L27/10817 ,  H01L27/10847 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/82 ,  H01L28/88 ,  H01L28/90 ,  H01L28/92

Abstract: Provided is a semiconductor device. The semiconductor device includes a capacitor structure including a plurality of lower electrodes, a dielectric layer that covers surfaces of the plurality of lower electrodes, and an upper electrode on the dielectric layer. The semiconductor device further includes a support structure that supports the plurality of lower electrodes. The support structure includes a first support region that covers sidewalls of one of the plurality of lower electrodes, and an opening that envelops the first support region when the semiconductor device is viewed in plan view.

公开(公告)号：US20160049460A1

公开(公告)日：2016-02-18

申请号：US14636397

申请日：2015-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Kim ,  Dae-Ik Kim ,  Seung-Jun Lee ,  Young-Seung Cho

IPC: H01L49/02

CPC classification number: H01L27/10814 ,  H01L27/10852 ,  H01L28/90

Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor devices include an interlayer insulating layer on a semiconductor substrate, contact pads on the semiconductor substrate and penetrating the interlayer insulating layer, a stopping insulating layer on the interlayer insulating layer, storage electrodes on the contact pads, upper supporters between upper parts of the storage electrodes, side supporters between the storage electrodes and the upper supporters, a capacitor dielectric layer on the storage electrodes, the side supporters, and the upper supporters, and a plate electrode on the capacitor dielectric layer.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括在半导体衬底上的层间绝缘层，半导体衬底上的接触焊盘并穿透层间绝缘层，层间绝缘层上的停止绝缘层，接触焊盘上的存储电极，上部部分之间的上部支撑 存储电极，存储电极和上支撑体之间的侧支撑体，存储电极上的电容器电介质层，侧支撑体和上支撑件，以及电容器介电层上的平板电极。

公开(公告)号：US09496266B2

公开(公告)日：2016-11-15

申请号：US14595834

申请日：2015-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Eun Kim ,  Young-Seung Cho ,  So-Hyun Park ,  Sang-Jo Yun

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10876 ,  H01L28/60 ,  H01L28/90

Abstract: A method of manufacturing a semiconductor device is provided. The method includes sequentially forming a mold layer and a preliminary support layer on a substrate, forming a plurality of lower electrodes through the preliminary support layer and the mold layer, removing a portion of the preliminary support layer between the plurality of lower electrodes to form a preliminary support layer pattern having an open area exposing a top surface of the mold layer, removing the mold layer to form a void between the substrate and the preliminary support layer pattern, filling the open area and the void with a sacrificial layer, and replacing the preliminary support layer pattern with a support pattern.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括在基板上依次形成模层和预备支撑层，通过预备支撑层和模层形成多个下电极，去除多个下电极之间的初步支撑层的一部分，形成 初步支撑层图案具有露出模具层的顶表面的开放区域，去除模具层以在基底和初步支撑层图案之间形成空隙，用牺牲层填充开放区域和空隙，并且将 具有支撑图案的初步支撑层图案。

公开(公告)号：US20160300763A1

公开(公告)日：2016-10-13

申请号：US15189697

申请日：2016-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Kim ,  Hoon Jeong ,  Jae-Hyun Kim ,  Dong-Won Lee ,  Jung-Gu Han ,  Ji-Hye Hwang

IPC: H01L21/768 ,  H01L23/528 ,  G11C5/06 ,  H01L27/105

CPC classification number: H01L21/76897 ,  G11C5/063 ,  H01L21/768 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10885

Abstract: Semiconductor devices are provided. A semiconductor device includes a bit line structure and a contact plug. The contact plug is adjacent a sidewall of the bit line structure and is on a sloped surface of the bit line structure. Moreover, in some embodiments, a level of the sloped surface of the bit line structure becomes lower as the sloped surface approaches the sidewall of the bit line structure.

公开(公告)号：US09406663B2

公开(公告)日：2016-08-02

申请号：US14161867

申请日：2014-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song ,  Kyung-Eun Kim ,  Jae-Kyun Park

IPC: H01L27/02 ,  H01L27/11 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L27/1104 ,  H01L2027/11812 ,  H01L2027/11838

Abstract: Semiconductor devices include a first gate pattern provided on the first active region, a second gate pattern over the first active region, a third gate pattern over the second active region, and a fourth gate pattern over the second active region. The second gate pattern is parallel to the first gate pattern in a first direction. The third gate pattern has an asymmetric shape to the first gate pattern with respect to the first direction, and the fourth gate pattern is parallel to the third gate pattern in the first direction, and has an asymmetric shape to the second gate pattern with respect to the first direction. MOS transistors having good properties may be provided in a narrow horizontal area. The MOS transistors may be used in highly stacked semiconductor devices.

Abstract translation: 半导体器件包括设置在第一有源区上的第一栅极图案，第一有源区上的第二栅极图案，第二有源区上的第三栅极图案，以及第二有源区上的第四栅极图案。 第二栅极图案在第一方向上平行于第一栅极图案。 第三栅极图案相对于第一方向具有与第一栅极图案不对称的形状，并且第四栅极图案在第一方向上平行于第三栅极图案，并且相对于第二栅极图案具有与第二栅极图案不对称的形状 第一个方向。 可以在窄的水平区域中提供具有良好性能的MOS晶体管。 MOS晶体管可以用于高度堆叠的半导体器件中。

公开(公告)号：US09318494B2

公开(公告)日：2016-04-19

申请号：US14692789

申请日：2015-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Kim ,  Dae-Ik Kim ,  Young-Seung Cho

IPC: H01L27/10 ,  H01L27/108 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L27/10885 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31144 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10888

Abstract: A method of forming a DRAM can include forming a plurality of transistors arranged in a first direction on a substrate and forming a bit line structure that extends in the first direction, where the bit line structure being electrically coupled to the plurality of transistors at respective locations in the first direction. A plurality of first landing pads an be formed at alternating ones of the respective locations having a first position in a second direction on the substrate. A plurality of second landing pads can be formed at intervening ones of the respective locations between the alternating ones of the respective locations, where the intervening ones of the respective locations having a second position in the second direction on the substrate wherein second position is shifted in the second direction relative to the first position.

Abstract translation: 形成DRAM的方法可以包括在衬底上形成沿第一方向布置的多个晶体管，并形成在第一方向上延伸的位线结构，其中位线结构在相应位置处电耦合到多个晶体管 在第一个方向。 多个第一着陆焊盘形成在相应位置的交替的位置处，在衬底上具有第二方向的第一位置。 可以在相应位置的交替位置之间的相应位置的中间位置形成多个第二着陆焊盘，其中相应位置中的中间位置具有在基板上的第二方向上的第二位置，其中第二位置被移动 相对于第一位置的第二方向。