公开(公告)号：US10121793B2

公开(公告)日：2018-11-06

申请号：US15083819

申请日：2016-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Kim ,  Yongkwan Kim ,  Semyeong Jang ,  Jaehyoung Choi ,  Yoosang Hwang ,  Bong-Soo Kim

IPC: H01L27/108

Abstract: A semiconductor device includes storage electrodes on a substrate and one or more supporters configured to couple one or more portions of the storage electrodes. The semiconductor device may include multiple non-intersecting supporters extending in parallel to a surface of the substrate. At least one supporter may have an upper surface that is substantially coplanar with upper surfaces of the storage electrodes. The storage electrodes may include a capacitor dielectric layer that conformally covers one or more surfaces of the storage electrodes and one or more supporters. A storage electrode may include upper and lower storage electrodes coupled together. The upper and lower storage electrodes may have different horizontal widths.

公开(公告)号：US09601494B2

公开(公告)日：2017-03-21

申请号：US14636397

申请日：2015-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Kim ,  Dae-Ik Kim ,  Seung-Jun Lee ,  Young-Seung Cho

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10814 ,  H01L27/10852 ,  H01L28/90

Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor devices include an interlayer insulating layer on a semiconductor substrate, contact pads on the semiconductor substrate and penetrating the interlayer insulating layer, a stopping insulating layer on the interlayer insulating layer, storage electrodes on the contact pads, upper supporters between upper parts of the storage electrodes, side supporters between the storage electrodes and the upper supporters, a capacitor dielectric layer on the storage electrodes, the side supporters, and the upper supporters, and a plate electrode on the capacitor dielectric layer.

公开(公告)号：US09196729B2

公开(公告)日：2015-11-24

申请号：US14254576

申请日：2014-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Jin Lee ,  Jun-Hee Lim ,  Kyung-Eun Kim

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L27/108

CPC classification number: H01L29/7838 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66477

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including an active region on a substrate, the active region being defined by a field region; gate trenches in the active region of the substrate; gate structures respectively formed in the gate trenches; and at least one carrier barrier layer in the substrate and under the gate trenches.

Abstract translation: 一种半导体器件和制造半导体器件的方法，所述器件包括在衬底上的有源区，所述有源区由场区限定; 在衬底的有源区中的栅极沟槽; 分别形成在栅极沟槽中的栅极结构; 以及衬底中的至少一个载流子阻挡层和栅极沟槽之下。

公开(公告)号：US09985033B2

公开(公告)日：2018-05-29

申请号：US15397842

申请日：2017-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Kyung-Eun Kim ,  Bong-Soo Kim ,  Ki-hyung Nam ,  Yoosang Hwang

IPC: H01L23/48 ,  H01L27/108 ,  H01L29/423

CPC classification number: H01L27/10811 ,  H01L27/10814 ,  H01L27/10847 ,  H01L29/4238

Abstract: A semiconductor device including a capacitor is provided. The semiconductor device includes lower electrodes, each of which includes a first electrode and a second electrode stacked in a first direction. The second electrode has a pillar shape that has a bar-type cross section having a longitudinal axis when viewed from a cross-sectional view taken along a plane defined by second and third directions perpendicular to the first direction.

公开(公告)号：US09871093B2

公开(公告)日：2018-01-16

申请号：US15383159

申请日：2016-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Kim ,  Ki-hyung Nam ,  Byung Yoon Kim ,  Bong-Soo Kim ,  Eunjung Kim ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L28/56 ,  H01L27/10808 ,  H01L27/10817 ,  H01L27/10847 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/82 ,  H01L28/88 ,  H01L28/90 ,  H01L28/92

Abstract: Provided is a semiconductor device. The semiconductor device includes a capacitor structure including a plurality of lower electrodes, a dielectric layer that covers surfaces of the plurality of lower electrodes, and an upper electrode on the dielectric layer. The semiconductor device further includes a support structure that supports the plurality of lower electrodes. The support structure includes a first support region that covers sidewalls of one of the plurality of lower electrodes, and an opening that envelops the first support region when the semiconductor device is viewed in plan view.

公开(公告)号：US09418998B2

公开(公告)日：2016-08-16

申请号：US14497649

申请日：2014-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Kim ,  Hoon Jeong ,  Jae-Hyun Kim ,  Dong-Won Lee ,  Jung-Gu Han ,  Ji-Hye Hwang

IPC: H01L23/528 ,  H01L27/105 ,  H01L21/768 ,  H01L27/108

CPC classification number: H01L21/76897 ,  G11C5/063 ,  H01L21/768 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10885

Abstract: Semiconductor devices are provided. A semiconductor device includes a bit line structure and a contact plug. The contact plug is adjacent a sidewall of the bit line structure and is on a sloped surface of the bit line structure. Moreover, in some embodiments, a level of the sloped surface of the bit line structure becomes lower as the sloped surface approaches the sidewall of the bit line structure.

Abstract translation: 提供半导体器件。 半导体器件包括位线结构和接触插头。 接触塞与位线结构的侧壁相邻，并且位于位线结构的倾斜表面上。 此外，在一些实施例中，当倾斜表面接近位线结构的侧壁时，位线结构的倾斜表面的水平变低。

公开(公告)号：US20160020213A1

公开(公告)日：2016-01-21

申请号：US14692789

申请日：2015-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Kim ,  Dae-Ik Kim ,  Young-Seung Cho

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L27/10885 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31144 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10888

Abstract: A method of forming a DRAM can include forming a plurality of transistors arranged in a first direction on a substrate and forming a bit line structure that extends in the first direction, where the bit line structure being electrically coupled to the plurality of transistors at respective locations in the first direction. A plurality of first landing pads an be formed at alternating ones of the respective locations having a first position in a second direction on the substrate. A plurality of second landing pads can be formed at intervening ones of the respective locations between the alternating ones of the respective locations, where the intervening ones of the respective locations having a second position in the second direction on the substrate wherein second position is shifted in the second direction relative to the first position.

Abstract translation: 形成DRAM的方法可以包括在衬底上形成沿第一方向布置的多个晶体管，并形成在第一方向上延伸的位线结构，其中位线结构在相应位置处电耦合到多个晶体管 在第一个方向。 多个第一着陆焊盘形成在相应位置的交替的位置处，在衬底上具有第二方向的第一位置。 可以在相应位置的交替位置之间的相应位置的中间位置形成多个第二着陆焊盘，其中相应位置中的中间位置具有在基板上的第二方向上的第二位置，其中第二位置被移动 相对于第一位置的第二方向。

公开(公告)号：US09786558B2

公开(公告)日：2017-10-10

申请号：US15189697

申请日：2016-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Kim ,  Hoon Jeong ,  Jae-Hyun Kim ,  Dong-Won Lee ,  Jung-Gu Han ,  Ji-Hye Hwang

IPC: H01L23/528 ,  H01L27/105 ,  H01L21/768 ,  G11C5/06 ,  H01L27/108

CPC classification number: H01L21/76897 ,  G11C5/063 ,  H01L21/768 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10885

Abstract: Semiconductor devices are provided. A semiconductor device includes a bit line structure and a contact plug. The contact plug is adjacent a sidewall of the bit line structure and is on a sloped surface of the bit line structure. Moreover, in some embodiments, a level of the sloped surface of the bit line structure becomes lower as the sloped surface approaches the sidewall of the bit line structure.

公开(公告)号：US20160020212A1

公开(公告)日：2016-01-21

申请号：US14595834

申请日：2015-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Eun Kim ,  Young-Seung Cho ,  So-Hyun Park ,  Sang-Jo Yun

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10876 ,  H01L28/60 ,  H01L28/90

Abstract: A method of manufacturing a semiconductor device is provided. The method includes sequentially forming a mold layer and a preliminary support layer on a substrate, forming a plurality of lower electrodes through the preliminary support layer and the mold layer, removing a portion of the preliminary support layer between the plurality of lower electrodes to form a preliminary support layer pattern having an open area exposing a top surface of the mold layer, removing the mold layer to form a void between the substrate and the preliminary support layer pattern, filling the open area and the void with a sacrificial layer, and replacing the preliminary support layer pattern with a support pattern.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括在基板上依次形成模层和预备支撑层，通过预备支撑层和模层形成多个下电极，去除多个下电极之间的初步支撑层的一部分，形成 初步支撑层图案具有露出模具层的顶表面的开放区域，去除模具层以在基板和预备支撑层图案之间形成空隙，用牺牲层填充开放区域和空隙，并且将 具有支撑图案的初步支撑层图案。

公开(公告)号：US20150228574A1

公开(公告)日：2015-08-13

申请号：US14497649

申请日：2014-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Kim ,  Hoon Jeong ,  Jae-Hyun Kim ,  Dong-Won Lee ,  Jung-Gu Han ,  Ji-Hye Hwang

IPC: H01L23/528 ,  H01L27/105

CPC classification number: H01L21/76897 ,  G11C5/063 ,  H01L21/768 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10885

Abstract: Semiconductor devices are provided. A semiconductor device includes a bit line structure and a contact plug. The contact plug is adjacent a sidewall of the bit line structure and is on a sloped surface of the bit line structure. Moreover, in some embodiments, a level of the sloped surface of the bit line structure becomes lower as the sloped surface approaches the sidewall of the bit line structure.

Abstract translation: 提供半导体器件。 半导体器件包括位线结构和接触插塞。 接触塞与位线结构的侧壁相邻，并且位于位线结构的倾斜表面上。 此外，在一些实施例中，当倾斜表面接近位线结构的侧壁时，位线结构的倾斜表面的水平变低。