公开(公告)号：US10714565B2

公开(公告)日：2020-07-14

申请号：US16593438

申请日：2019-10-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-hyung Nam ,  Bong-Soo Kim ,  Yoosang Hwang

IPC: H01L29/41 ,  H01L49/02 ,  H01L27/108 ,  H01L21/311 ,  H01L21/285 ,  H01L21/02 ,  H01L21/3213 ,  H01L27/112

Abstract: A semiconductor device including a plurality of pillars on a semiconductor substrate; and a support pattern in contact with some lateral surfaces of the pillars and connecting the pillars with one another, wherein the support pattern includes openings that expose other lateral surfaces of the pillars, each of the pillars includes a first pillar upper portion in contact with the support pattern and a second pillar upper portion spaced apart from the support pattern, and the second pillar upper portion has a concave slope.

公开(公告)号：US09985033B2

公开(公告)日：2018-05-29

申请号：US15397842

申请日：2017-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Kyung-Eun Kim ,  Bong-Soo Kim ,  Ki-hyung Nam ,  Yoosang Hwang

IPC: H01L23/48 ,  H01L27/108 ,  H01L29/423

CPC classification number: H01L27/10811 ,  H01L27/10814 ,  H01L27/10847 ,  H01L29/4238

Abstract: A semiconductor device including a capacitor is provided. The semiconductor device includes lower electrodes, each of which includes a first electrode and a second electrode stacked in a first direction. The second electrode has a pillar shape that has a bar-type cross section having a longitudinal axis when viewed from a cross-sectional view taken along a plane defined by second and third directions perpendicular to the first direction.

公开(公告)号：US09871093B2

公开(公告)日：2018-01-16

申请号：US15383159

申请日：2016-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Kim ,  Ki-hyung Nam ,  Byung Yoon Kim ,  Bong-Soo Kim ,  Eunjung Kim ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L28/56 ,  H01L27/10808 ,  H01L27/10817 ,  H01L27/10847 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/82 ,  H01L28/88 ,  H01L28/90 ,  H01L28/92

Abstract: Provided is a semiconductor device. The semiconductor device includes a capacitor structure including a plurality of lower electrodes, a dielectric layer that covers surfaces of the plurality of lower electrodes, and an upper electrode on the dielectric layer. The semiconductor device further includes a support structure that supports the plurality of lower electrodes. The support structure includes a first support region that covers sidewalls of one of the plurality of lower electrodes, and an opening that envelops the first support region when the semiconductor device is viewed in plan view.

公开(公告)号：US10483346B2

公开(公告)日：2019-11-19

申请号：US16115690

申请日：2018-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-hyung Nam ,  Bong-Soo Kim ,  Yoosang Hwang

IPC: H01L29/41 ,  H01L49/02 ,  H01L27/108 ,  H01L21/311 ,  H01L21/285 ,  H01L21/02 ,  H01L21/3213 ,  H01L27/112

Abstract: A semiconductor device including a plurality of pillars on a semiconductor substrate; and a support pattern in contact with some lateral surfaces of the pillars and connecting the pillars with one another, wherein the support pattern includes openings that expose other lateral surfaces of the pillars, each of the pillars includes a first pillar upper portion in contact with the support pattern and a second pillar upper portion spaced apart from the support pattern, and the second pillar upper portion has a concave slope.

公开(公告)号：US08981468B2

公开(公告)日：2015-03-17

申请号：US13943208

申请日：2013-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-hyung Nam ,  Yong Kwan Kim ,  Chan Ho Park ,  Pulunsol Cho

IPC: H01L29/78 ,  H01L29/66 ,  H01L45/00 ,  H01L27/22

CPC classification number: H01L29/7831 ,  H01L27/228 ,  H01L27/2454 ,  H01L29/66484 ,  H01L45/06 ,  H01L45/085 ,  H01L45/144 ,  H01L45/145

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device includes active portions defined in a semiconductor substrate, a device isolation pattern in a trench formed between the active portions, a gate electrode in a gate recess region crossing the active portions and the device isolation pattern, a gate dielectric layer between the gate electrode and an inner surface of the gate recess region, and a first ohmic pattern and a second ohmic pattern on each of the active portions at both sides of the gate electrode, respectively. The first and second ohmic patterns include a metal-semiconductor compound, and a top surface of the device isolation pattern at both sides of the gate recess region is recessed to be lower than a level of a top surface of the semiconductor substrate.

Abstract translation: 公开了半导体器件及其制造方法。 半导体器件包括限定在半导体衬底中的有源部分，在有源部分之间形成的沟槽中的器件隔离图案，与有源部分交叉的栅极凹部区域中的栅极电极和器件隔离图案，栅极电介质层 电极和栅极凹陷区域的内表面，以及分别在栅电极两侧的每个有源部分上的第一欧姆图案和第二欧姆图案。 第一和第二欧姆模式包括金属半导体化合物，并且栅极凹部区域的两侧的器件隔离图案的顶表面凹陷以低于半导体衬底的顶表面的电平。