公开(公告)号：US20250016980A1

公开(公告)日：2025-01-09

申请号：US18629799

申请日：2024-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok Lee ,  Bongsoo Kim ,  Yongkwan Kim ,  Jongmin Kim ,  Taejin Park ,  Chansic Yoon ,  Jinwoo Han

IPC: H10B12/00

Abstract: A semiconductor device includes an active array in which a plurality of active patterns are arranged on a substrate; a gate structure extending in a first direction and crossing central portions of the active patterns; a bit line structure contacting first portions of the active patterns adjacent to a first sidewall of the gate structure and extending in a second direction; and a capacitor electrically connected to a second portion of each of the active patterns adjacent to a second sidewall of the gate structure. In a plan view, an upper end portion of each of the active patterns and a lower end portion of each of the active patterns are arranged to be spaced apart in a third direction oblique with respect to the first direction. The active patterns arranged side by side in the second direction form an active column.

公开(公告)号：US09847278B2

公开(公告)日：2017-12-19

申请号：US15095327

申请日：2016-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Kim ,  Yongkwan Kim ,  Semyeong Jang ,  Jaehyoung Choi ,  Yoosang Hwang ,  Bong-Soo Kim

IPC: H01L21/70 ,  H01L21/76 ,  H01L23/482 ,  H01L29/06 ,  H01L21/762 ,  H01L21/768 ,  H01L27/108 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/4821 ,  H01L21/76264 ,  H01L21/7682 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L29/0649

Abstract: A semiconductor device includes first and second bit line structures on a substrate and spaced apart from each other, a via plug partially filling between the first and second bit line structures, a via pad in contact with an upper surface of the via plug and an upper sidewall of the first bit line structure, the via pad being spaced apart from an upper portion of the second bit line structure, a first cavity filled with air being between the via plug and the first bit line structure and a second cavity filled with air between the via plug and the second bit line structure, A gap capping spacer having a first portion on the upper sidewall of the first bit line structure and a second portion covers the first air spacer. A horizontal width of the first portion is smaller than that of the second portion.

公开(公告)号：US10447997B2

公开(公告)日：2019-10-15

申请号：US15417563

申请日：2017-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kisuk Sung ,  Yongchan Keh ,  Yongkwan Kim ,  Sungsoon Kim ,  Hyo-Won Kim ,  Byeonghoon Park ,  Jungkee Lee ,  Kihuk Lee

IPC: H04N13/20 ,  H05B37/02 ,  G06F3/01 ,  G06T7/50 ,  H04N13/25 ,  G06T7/521 ,  G01S17/02 ,  G01S17/66 ,  G01S17/89 ,  G01S7/484 ,  G01S7/497 ,  G01S7/491 ,  H04N13/243 ,  H04N13/254 ,  H04N13/271 ,  H04N13/296 ,  G01S17/08

Abstract: A method and apparatus of example embodiments are related to photographing using a plurality of sensors in an electronic device. The electronic device includes a plurality of output units comprising output circuitry configured to output an identification signal to an external object, a sensor configured to acquire an identification signal that is a reflection of the identification signal from an external object, and a processor. The processor is configured to determine a first state of the external object, based on the reflected identification signal, to designate the plurality of output units as a first subset and a second subset, based at least on the first state of the external object, and to differently control the first subset and the second subset to output the identification signal.

公开(公告)号：US10121793B2

公开(公告)日：2018-11-06

申请号：US15083819

申请日：2016-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Kim ,  Yongkwan Kim ,  Semyeong Jang ,  Jaehyoung Choi ,  Yoosang Hwang ,  Bong-Soo Kim

IPC: H01L27/108

Abstract: A semiconductor device includes storage electrodes on a substrate and one or more supporters configured to couple one or more portions of the storage electrodes. The semiconductor device may include multiple non-intersecting supporters extending in parallel to a surface of the substrate. At least one supporter may have an upper surface that is substantially coplanar with upper surfaces of the storage electrodes. The storage electrodes may include a capacitor dielectric layer that conformally covers one or more surfaces of the storage electrodes and one or more supporters. A storage electrode may include upper and lower storage electrodes coupled together. The upper and lower storage electrodes may have different horizontal widths.