知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

10 records (took 0.015 seconds)

    METHODS OF FORMING POSITIONED LANDING PADS AND SEMICONDUCTOR DEVICES INCLUDING THE SAME
    1.
    发明申请
    METHODS OF FORMING POSITIONED LANDING PADS AND SEMICONDUCTOR DEVICES INCLUDING THE SAME 有权
    形成定位线的方法和包括其的半导体器件

    公开(公告)号：US20160020213A1

    公开(公告)日：2016-01-21

    申请号：US14692789

    申请日：2015-04-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung-Eun Kim ,  Dae-Ik Kim ,  Young-Seung Cho

    IPC: H01L27/108 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02

    CPC classification number: H01L27/10885 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31144 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10888

    Abstract: A method of forming a DRAM can include forming a plurality of transistors arranged in a first direction on a substrate and forming a bit line structure that extends in the first direction, where the bit line structure being electrically coupled to the plurality of transistors at respective locations in the first direction. A plurality of first landing pads an be formed at alternating ones of the respective locations having a first position in a second direction on the substrate. A plurality of second landing pads can be formed at intervening ones of the respective locations between the alternating ones of the respective locations, where the intervening ones of the respective locations having a second position in the second direction on the substrate wherein second position is shifted in the second direction relative to the first position.

    Abstract translation: 形成DRAM的方法可以包括在衬底上形成沿第一方向布置的多个晶体管，并形成在第一方向上延伸的位线结构，其中位线结构在相应位置处电耦合到多个晶体管 在第一个方向。 多个第一着陆焊盘形成在相应位置的交替的位置处，在衬底上具有第二方向的第一位置。 可以在相应位置的交替位置之间的相应位置的中间位置形成多个第二着陆焊盘，其中相应位置中的中间位置具有在基板上的第二方向上的第二位置，其中第二位置被移动 相对于第一位置的第二方向。

    Semiconductor device including a capacitor and a method of manufacturing the same
    2.
    发明授权
    Semiconductor device including a capacitor and a method of manufacturing the same 有权
    包括电容器的半导体器件及其制造方法

    公开(公告)号：US09496266B2

    公开(公告)日：2016-11-15

    申请号：US14595834

    申请日：2015-01-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyung-Eun Kim ,  Young-Seung Cho ,  So-Hyun Park ,  Sang-Jo Yun

    IPC: H01L27/108 ,  H01L49/02

    CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10876 ,  H01L28/60 ,  H01L28/90

    Abstract: A method of manufacturing a semiconductor device is provided. The method includes sequentially forming a mold layer and a preliminary support layer on a substrate, forming a plurality of lower electrodes through the preliminary support layer and the mold layer, removing a portion of the preliminary support layer between the plurality of lower electrodes to form a preliminary support layer pattern having an open area exposing a top surface of the mold layer, removing the mold layer to form a void between the substrate and the preliminary support layer pattern, filling the open area and the void with a sacrificial layer, and replacing the preliminary support layer pattern with a support pattern.

    Abstract translation: 提供一种制造半导体器件的方法。 该方法包括在基板上依次形成模层和预备支撑层，通过预备支撑层和模层形成多个下电极，去除多个下电极之间的初步支撑层的一部分，形成 初步支撑层图案具有露出模具层的顶表面的开放区域，去除模具层以在基底和初步支撑层图案之间形成空隙，用牺牲层填充开放区域和空隙，并且将 具有支撑图案的初步支撑层图案。

    SEMICONDUCTOR DEVICES INCLUDING CAPACITORS AND METHODS OF MANUFACTURING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING CAPACITORS AND METHODS OF MANUFACTURING THE SAME 审中-公开
    包括电容器的半导体器件及其制造方法

    公开(公告)号：US20160225845A1

    公开(公告)日：2016-08-04

    申请号：US15087349

    申请日：2016-03-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-Seung Cho ,  Sung-Eui Kim ,  Ji-Young Kim ,  Hoon Jeong ,  Chan-Won Kim ,  Jong-Bom Seo ,  Seung-Jun Lee ,  Jun-Soo Lee

    IPC: H01L49/02

    CPC classification number: H01L28/88 ,  H01L21/764 ,  H01L27/10808 ,  H01L27/10811 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/90

    Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.

    Abstract translation: 半导体器件包括第一电容器结构，第二电容器结构和绝缘图案。 第一电容器结构包括顺序堆叠在基板上的第一下电极，第一电介质层和第一上电极。 第二电容器结构包括第二下电极，第二电介质层和顺序堆叠在基板上并与第一电容器结构相邻的第二上电极。 绝缘图案部分地填充第一和第二电容器结构之间的空间，并且在绝缘图案上的第一和第二电容器结构之间形成气隙。

    Methods of forming positioned landing pads and semiconductor devices including the same
    4.
    发明授权
    Methods of forming positioned landing pads and semiconductor devices including the same 有权
    形成定位的着陆垫和包括其的半导体器件的方法

    公开(公告)号：US09318494B2

    公开(公告)日：2016-04-19

    申请号：US14692789

    申请日：2015-04-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung-Eun Kim ,  Dae-Ik Kim ,  Young-Seung Cho

    IPC: H01L27/10 ,  H01L27/108 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311

    CPC classification number: H01L27/10885 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31144 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10888

    Abstract: A method of forming a DRAM can include forming a plurality of transistors arranged in a first direction on a substrate and forming a bit line structure that extends in the first direction, where the bit line structure being electrically coupled to the plurality of transistors at respective locations in the first direction. A plurality of first landing pads an be formed at alternating ones of the respective locations having a first position in a second direction on the substrate. A plurality of second landing pads can be formed at intervening ones of the respective locations between the alternating ones of the respective locations, where the intervening ones of the respective locations having a second position in the second direction on the substrate wherein second position is shifted in the second direction relative to the first position.

    Abstract translation: 形成DRAM的方法可以包括在衬底上形成沿第一方向布置的多个晶体管，并形成在第一方向上延伸的位线结构，其中位线结构在相应位置处电耦合到多个晶体管 在第一个方向。 多个第一着陆焊盘形成在相应位置的交替的位置处，在衬底上具有第二方向的第一位置。 可以在相应位置的交替位置之间的相应位置的中间位置形成多个第二着陆焊盘，其中相应位置中的中间位置具有在基板上的第二方向上的第二位置，其中第二位置被移动 相对于第一位置的第二方向。

    Semiconductor devices including capacitors and methods of manufacturing the same
    5.
    发明授权
    Semiconductor devices including capacitors and methods of manufacturing the same 有权
    包括电容器的半导体器件及其制造方法

    公开(公告)号：US09431476B2

    公开(公告)日：2016-08-30

    申请号：US15087349

    申请日：2016-03-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-Seung Cho ,  Sung-Eui Kim ,  Ji-Young Kim ,  Hoon Jeong ,  Chan-Won Kim ,  Jong-Bom Seo ,  Seung-Jun Lee ,  Jun-Soo Lee

    IPC: H01L21/00 ,  H01L49/02 ,  H01L27/108 ,  H01L21/764

    CPC classification number: H01L28/88 ,  H01L21/764 ,  H01L27/10808 ,  H01L27/10811 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/90

    Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.

    Abstract translation: 半导体器件包括第一电容器结构，第二电容器结构和绝缘图案。 第一电容器结构包括顺序堆叠在基板上的第一下电极，第一电介质层和第一上电极。 第二电容器结构包括第二下电极，第二电介质层和顺序堆叠在基板上并与第一电容器结构相邻的第二上电极。 绝缘图案部分地填充第一和第二电容器结构之间的空间，并且在绝缘图案上的第一和第二电容器结构之间形成气隙。

    Semiconductor Devices Having a Supporter and Methods of Fabricating the Same
    6.
    发明申请
    Semiconductor Devices Having a Supporter and Methods of Fabricating the Same 有权
    具有支持者的半导体器件及其制造方法

    公开(公告)号：US20160049460A1

    公开(公告)日：2016-02-18

    申请号：US14636397

    申请日：2015-03-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung-Eun Kim ,  Dae-Ik Kim ,  Seung-Jun Lee ,  Young-Seung Cho

    IPC: H01L49/02

    CPC classification number: H01L27/10814 ,  H01L27/10852 ,  H01L28/90

    Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor devices include an interlayer insulating layer on a semiconductor substrate, contact pads on the semiconductor substrate and penetrating the interlayer insulating layer, a stopping insulating layer on the interlayer insulating layer, storage electrodes on the contact pads, upper supporters between upper parts of the storage electrodes, side supporters between the storage electrodes and the upper supporters, a capacitor dielectric layer on the storage electrodes, the side supporters, and the upper supporters, and a plate electrode on the capacitor dielectric layer.

    Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括在半导体衬底上的层间绝缘层，半导体衬底上的接触焊盘并穿透层间绝缘层，层间绝缘层上的停止绝缘层，接触焊盘上的存储电极，上部部分之间的上部支撑 存储电极，存储电极和上支撑体之间的侧支撑体，存储电极上的电容器电介质层，侧支撑体和上支撑件，以及电容器介电层上的平板电极。

    SEMICONDUCTOR DEVICE INCLUDING A CAPACITOR AND A METHOD OF MANUFACTURING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING A CAPACITOR AND A METHOD OF MANUFACTURING THE SAME 有权
    包括电容器的半导体器件及其制造方法

    公开(公告)号：US20160020212A1

    公开(公告)日：2016-01-21

    申请号：US14595834

    申请日：2015-01-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyung-Eun Kim ,  Young-Seung Cho ,  So-Hyun Park ,  Sang-Jo Yun

    IPC: H01L27/108

    CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10876 ,  H01L28/60 ,  H01L28/90

    Abstract: A method of manufacturing a semiconductor device is provided. The method includes sequentially forming a mold layer and a preliminary support layer on a substrate, forming a plurality of lower electrodes through the preliminary support layer and the mold layer, removing a portion of the preliminary support layer between the plurality of lower electrodes to form a preliminary support layer pattern having an open area exposing a top surface of the mold layer, removing the mold layer to form a void between the substrate and the preliminary support layer pattern, filling the open area and the void with a sacrificial layer, and replacing the preliminary support layer pattern with a support pattern.

    Abstract translation: 提供一种制造半导体器件的方法。 该方法包括在基板上依次形成模层和预备支撑层，通过预备支撑层和模层形成多个下电极，去除多个下电极之间的初步支撑层的一部分，形成 初步支撑层图案具有露出模具层的顶表面的开放区域，去除模具层以在基板和预备支撑层图案之间形成空隙，用牺牲层填充开放区域和空隙，并且将 具有支撑图案的初步支撑层图案。

    SEMICONDUCTOR MEMORY DEVICE
    9.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240237334A1

    公开(公告)日：2024-07-11

    申请号：US18350323

    申请日：2023-07-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kang In Kim ,  Kyoung Hwan Kim ,  Young Woo Son ,  Sang-Bin Ahn ,  Sang Min Lee ,  Young-Seung Cho

    IPC: H10B12/00

    CPC classification number: H10B12/50 ,  H10B12/315

    Abstract: A semiconductor memory device with improved performance and reliability is provided. The semiconductor memory device includes a substrate having a cell region and a peripheral region, a cell region isolation layer that separates the cell region from the peripheral region, and a plurality of cell gate structures, each including a cell gate electrode that extends in a first direction. The cell region includes a plurality of active areas that extend in a second direction different from the first direction, and are between a respective cell element isolation layer and the cell region isolation layer. Each of the active areas includes a first portion and a second portion separated by the cell gate structure, the second portion of the active area is on both sides of a respective one of the first portion of the active area. The active areas includes a normal active area and a dummy active area.

Patent Agency Ranking