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公开(公告)号：US20130128671A1
公开(公告)日：2013-05-23
申请号：US13625114
申请日：2012-09-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SEUNG-HWAN SHIN , KITAE PARK , HYUN-WOOK PARK , JUN-HEE LEE
IPC: G11C16/10
CPC classification number: G11C16/10 , G11C11/5621 , G11C16/06
Abstract: Disclosed is a flash memory device and programming method that includes; receiving buffer data and determining between a high-speed mode and a reliability mode for buffer data, and upon determining the reliability mode storing the buffer data in a first buffer region, and upon determining the high-speed mode storing the buffer data in a second buffer region. The memory cell array of the flash memory including a main region and a separately designated buffer region divided into the first buffer region and second buffer region.
Abstract translation: 公开了一种闪速存储器件和编程方法，包括： 接收缓冲器数据，并在缓冲器数据的高速模式和可靠性模式之间确定，并且在确定将缓冲器数据存储在第一缓冲区域中的可靠性模式时，并且在确定将第二缓冲器数据存储在第二缓冲器数据中的高速模式 缓冲区。 闪速存储器的存储单元阵列包括分为第一缓冲区域和第二缓冲区域的主区域和单独指定的缓冲区域。
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12.发明申请公开(公告)号：US20170271013A1
公开(公告)日：2017-09-21
申请号：US15609761
申请日：2017-05-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SANG-WAN NAM , KITAE PARK
CPC classification number: G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/3427
Abstract: A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line.
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Patent Agency Ranking
公开(公告)号：US20170062046A1
公开(公告)日：2017-03-02
申请号：US15351552
申请日：2016-11-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SANG-WON PARK , DONGKYO SHIM , KITAE PARK , SANG-WON SHIM
CPC classification number: G11C11/5642 , G11C8/08 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/3459 , G11C29/021 , G11C29/028
Abstract: A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory cell array, and control logic including a time control unit that determines a word line setup time for the word line in relation to the second setup voltage based on a difference between the first and second setup voltages.
Abstract translation: 非易失性存储器件包括：电压发生器，其向存储单元阵列的字线依次提供第一设定电压和第二设定电压;以及控制逻辑，包括时间控制单元，所述时间控制单元确定所述字线的字线建立时间 基于所述第一和第二设定电压之间的差，将所述第二设置电压提供给所述第二设置电压。
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14.发明申请NONVOLATILE MEMORY DEVICES AND METHODS OF PROGRAMMING NONVOLATILE MEMORY DEVICES 审中-公开非易失性存储器件和编程非易失性存储器件的方法公开(公告)号：US20150348633A1
公开(公告)日：2015-12-03
申请号：US14747786
申请日：2015-06-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： YOUNGSUN SONG , BOGEUN KIM , OHSUK KWON , KITAE PARK , SEUNG-HWAN SHIN , SANGYONG YOON , MOOSUNG KIM , HYUNJUN YOON
CPC classification number: G11C16/12 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3459
Abstract: A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog bit counting unit which counts the currents, a digital adding unit which calculates an accumulated sum of the counting result, a pass/fail checking unit which outputs a pass signal or fail signal according to the calculation result, and a control unit controlling a program operation.
Abstract translation: 非易失性存储器件包括存储单元阵列，输出验证读取结果的页面缓冲器单元，产生参考电流信号的参考电流产生单元，根据验证读取结果输出电流的页面缓冲器解码单元。 非易失性存储装置还包括对电流进行计数的模拟比特计数单元，计算计数结果的累积和的数字加法单元，根据计算结果输出通过信号或失败信号的通过/失败检查单元， 以及控制程序操作的控制单元。
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15.发明申请NONVOLATILE MEMORY DEVICES AND METHODS OF PROGRAMMING NONVOLATILE MEMORY DEVICES 审中-公开非易失性存储器件和编程非易失性存储器件的方法公开(公告)号：US20140376312A1
公开(公告)日：2014-12-25
申请号：US14316023
申请日：2014-06-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： YOUNGSUN SONG , BOGEUN KIM , OHSUK KWON , KITAE PARK , SEUNG-HWAN SHIN , SANGYONG YOON
CPC classification number: G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/08 , G11C16/34 , G11C16/3459
Abstract: A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog bit counting unit which counts the currents, a digital adding unit which calculates an accumulated sum of the counting result, a pass/fail checking unit which outputs a pass signal or fail signal according to the calculation result, and a control unit controlling a program operation.
Abstract translation: 非易失性存储器件包括存储单元阵列，输出验证读取结果的页面缓冲器单元，产生参考电流信号的参考电流产生单元，根据验证读取结果输出电流的页面缓冲器解码单元。 非易失性存储装置还包括对电流进行计数的模拟比特计数单元，计算计数结果的累积和的数字加法单元，根据计算结果输出通过信号或失败信号的通过/失败检查单元， 以及控制程序操作的控制单元。
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16.发明申请公开(公告)号：US20140153330A1
公开(公告)日：2014-06-05
申请号：US14088511
申请日：2013-11-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： HYUN JUN YOON , JAEYONG JEONG , MYUNG-HOON CHOI , KITAE PARK
CPC classification number: G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/3404 , G11C16/3422
Abstract: An operating method for a non-volatile memory device includes applying first and second read voltages to a first word line to perform a read operation; counting first memory cells each having a threshold voltage belonging to a first voltage range between the first read voltage and the second read voltage; applying a third read voltage to the first word line sequentially after applying the second read voltage to count second memory cells each having a second threshold voltage belonging to a voltage range between the second read voltage and the third read voltage; comparing the number of first memory cells counted and the number of second memory cells counted; determining a fourth read voltage based on a result of the comparing; and applying the fourth read voltage to the first word line sequentially after applying the third read voltage.
Abstract translation: 一种用于非易失性存储器件的操作方法包括：将第一和第二读取电压施加到第一字线以执行读取操作; 计数每个具有属于第一读取电压和第二读取电压之间的第一电压范围的阈值电压的第一存储器单元; 在施加第二读取电压以对具有属于第二读取电压和第三读取电压之间的电压范围的第二阈值电压的第二存储器单元计数时，顺序地向第一字线施加第三读取电压; 比较计数的第一存储器单元的数量和计数的第二存储单元的数量; 基于所述比较的结果确定第四读取电压; 以及在施加第三读取电压之后，将第四读取电压顺序地施加到第一字线。
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公开(公告)号：US20140025866A1
公开(公告)日：2014-01-23
申请号：US13915676
申请日：2013-06-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： BOH-CHANG KIM , DONGKYO SHIM , KITAE PARK
IPC: G06F12/02
CPC classification number: G06F12/0246 , G11C11/5642 , G11C16/10 , G11C16/3418 , G11C16/3459
Abstract: A method of programming data in a nonvolatile memory via a first memory cell group and a second memory cell group in a page of memory cells includes; executing a first program operation that programs the first memory cell group with a first program voltage that is stepwise adjusted by a first increment over successive programming loop iterations, and thereafter executing a second program operation that programs the second memory cell with a second program voltage that is stepwise adjusted by a second increment over successive programming loop iterations, wherein the first program voltage is different from the second program voltage.
Abstract translation: 一种在存储单元的页面中经由第一存储单元组和第二存储单元组在非易失性存储器中编程数据的方法包括： 执行第一编程操作，其以在连续编程循环迭代中由第一增量逐步调整的第一编程电压对第一存储单元组进行编程，然后执行第二编程操作，其以第二编程电压编程第二存储单元， 在连续的编程循环迭代中通过第二增量逐步调整，其中第一编程电压与第二编程电压不同。
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